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| 8-core | 4 high-performance Firestorm | 4 energy-efficient Icestorm |
| Speed | 3.2 GHz | 2.064 GHz |
| L1 cache | 192 KB instructions /128 KB data | 128 KB instructions / 64 KB data |
| L2 cache | 12 MB | 4 MB |
| 8-core | 4 high-performance Avalanche | 4 energy-efficient Blizzard |
| Speed | 3.49 GHz | 2.424 GHz |
| L1 cache | 192 KB instructions / 128 KB data | 128 KB instructions / 64 data |
| L2 cache | 16 MB | 4 MB |
| 8-core | 4 high-performance Everest (V2) | 4 energy-efficient Sawtooth (V2) |
| Speed | 4.05 GHz | 2.75 GHz |
| L1 cache | 192 KB instructions / 128 KB data | 128 KB instructions / 64 data |
| L2 cache | 16 MB | 4 MB |
| 10-core | 4 high-performance Everest (V3) | 6 energy-efficient Sawtooth (V3) |
| Speed | 4.41 GHz | 2.89 GHz |
| L1 cache | 192 KB instructions / 128 KB data | 128 KB instructions / 64 KB data |
| L2 cache | 16 MB | 4 MB |
| 10-core | 4 high-performance Everest (V4) | 6 energy-efficient Sawtooth (V4) |
| Speed | 4.46 GHz | 3.04 GHz |
| L1 cache | 192 KB instructions / 128 KB data | 128 KB instructions / 64 KB data |
| L2 cache | 22 MB | 6 MB |
No, it's just a compilation of specs rarely found al all together in one place.ok?
Is there a point you're trying to make?
Apple M4 (2024)
APL1206 (Donan, T8132)
TSMC N3E 3nm
28 billion transistors
CPU
Apple designed ARMv9.2-A
10-core big.LITTLE
Core designs from A18/A18 Pro
10-core 4 high-performance Everest (V3) 6 energy-efficient Sawtooth (V3) Speed 4.41 GHz 2.89 GHz L1 cache 192 KB instructions / 128 KB data 128 KB instructions / 64 KB data L2 cache 16 MB 4 MB
GPU
Apple G16G Apple 10 family integrated graphics 10 cores
160 Execution Units
1280 Arithmetic Logic Units
30,720 threads
1.58 GHz
4.32 TFLOPs (FP32)
16 Execution Units per core
8 Arithmetic Logic Units per Execution Unit
Dynamic Caching, Mesh Shading and Ray Tracing
Memory
Unified 128-bit 7,500 MT/s LPDDR5X SDRAM at 120 GB/s 3,750 MHz
Up to 32 GB
Other
Neural Engine 16-core 38 trillion operations per second 7th gen (H16x_Leto_J7x)
PCIe 4.0 storage controller up to 2 TB SSD
3x USB-C 4 controller with Thunderbolt 4/USB 4 support (40 Gb/s)
2x USB 3.0 Type-C (10 Gb/s)
Secure Enclave and Image Signal processor
Video codec encoding support for 8K HEVC and 8K H.264
Video codec decoding support for 8K ProRes, 8K HEVC, 8K H.264, VP9, AV1 and JPEG
HDMI 2.1
One 8K display at 60Hz or one 4K display at 240Hz Thunderbolt or HDMI
Wi-Fi 6E up to 2.4 Gbit/s 2x2
Bluetooth 5.3
I think you mean: thanks for compiling all of this information for us!ok?
Is there a point you're trying to make?
This is a forum, not a database. All of this information is available elsewhere, on sites that are actually built for that purpose. This is just post count padding.I think you mean: thanks for compiling all of this information for us!
I'll check back on those numbers later and will update the post if necessary, thanks for sharing your observation.I don't think the TFLOPS calculation is right:
1280*1.58*2/1000 = 4.0448 TFLOPS
And the M5 is even more off. The only thing that changed is a minor clock speed bump but a nearly 20% increase in TFLOPS? Why?
Also I'm not 100% what the execution unit is here? I was under the impression Apple had 4 x execution units of 32 FP32 units each, not 2 x 64. Unless there is another control structure below what they are calling the execution unit? @leman?
I'll check back on those numbers later and will update the post if necessary, thanks for sharing your observation.![]()
Whenever someone reports TFLOPS it should be peak, the theoretical throughput of the number of FP32 units x clock speed x 2, unless otherwise stated. The issue here is the numbers being reported are actually even above the peak theoretical value, which is not possible. So even from a perspective of peak vs sustained/practical, it doesn't really matter, the reported TFLOPS have issues starting with the M3.ok, peak flop value or sustainable (in bus widths, stack length, and other memory considerations etc)
I've edited the TFLOPS for M2, M3 and M4 according to these sources, M5 already matched the source:I don't think the TFLOPS calculation is right:
1280*1.58*2/1000 = 4.0448 TFLOPS
And the M5 is even more off. The only thing that changed is a minor clock speed bump but a nearly 20% increase in TFLOPS? Why?
Also I'm not 100% what the execution unit is here? I was under the impression Apple had 4 x execution units of 32 FP32 units each, not 2 x 64. Unless there is another control structure below what they are calling the execution unit? @leman?
Wikipedia lists the base M1 as having ProRes decode but not encode. And what does "The M1 is entirely CPU/GPU" mean?The M1 chip doesn’t have ProRes hardware acceleration. Only the subsequent chips have that.
The M1 is entirely CPU/GPU…
Fixed! Thank you!The M1 chip doesn’t have ProRes hardware acceleration. Only the subsequent chips have that.
The M1 is entirely CPU/GPU…
So Wikipedia is wrong on the M1 having a ProRes decoder?Fixed! Thank you!