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ksj1

macrumors 6502
Original poster
Jul 17, 2018
294
535
It will be interesting to see where it lands.

My suspicion is that they will use a CLOS fabric between X number of SOC's, though that seems non-trivial. Any other ideas?

Edit - Non-trivial, but frequently done in supercomputer clusters.
 

Gnattu

macrumors 65816
Sep 18, 2020
1,107
1,672
It could also be mesh, which could be easier to implement as they do not need a high-bandwidth switch for all SoCs.

My biggest question would be how do they incorporate the UMA programming model into this multi-SoC approach if it is really happening. Traditionally, programs need to be NUMA-aware to (use the best effort to) avoid data been accessed across NUMA domains because such operation is much slower than accessing data in its own NUMA-domain. This is still a problem in AMD's huge multi-die EPYC processors at least for some use case despite AMD's super-fast on-package fabric, and that's why EPYC processors can be configured to expose multiple NUMA domains instead of one.
 

ksj1

macrumors 6502
Original poster
Jul 17, 2018
294
535
It could also be mesh, which could be easier to implement as they do not need a high-bandwidth switch for all SoCs.

My biggest question would be how do they incorporate the UMA programming model into this multi-SoC approach if it is really happening. Traditionally, programs need to be NUMA-aware to (use the best effort to) avoid data been accessed across NUMA domains because such operation is much slower than accessing data in its own NUMA-domain. This is still a problem in AMD's huge multi-die EPYC processors at least for some use case despite AMD's super-fast on-package fabric, and that's why EPYC processors can be configured to expose multiple NUMA domains instead of one.
I think they have more than enough resources to develop and implement a high speed, low power switch.
 
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