corbin_a2 said:
So why is the G4 stuck at 167MHz?
Well, a 1GHz G5 bus is actually two DDR 250MHz buses, one each direction. If the G4 had DDR support, it would be marketed as a 333MHz bus chip. Supposedly it supports a 200MHz bus setting as well, but Apple hasn't used this (or possibly it hasn't been released yet).
Technically speaking, the MPX bus protocol that the G4 uses is quite complex compared to the G5's. It's designed to allow multiple devices attached to the same bus, fairly long wires, etc... The G5's bus is a very short very simple 1 directional 1-1 link, using some fairly sophisticated signalling techniques. As a result, it's able to run very fast, although the northbridge chip it hooks up to ends up being quite hot due to having to run fast to keep up with it.
The easiest upgrade (I think, anyway. I'm not a professional) would be to add DDR support to the MPXbus, and it's unclear why this hasn't been done. My guess is that they decided that the MPXbus was dead, and were moving on to an integrated memory controller, but it took a lot longer than they expected. A G4 with a high speed integrated memory controller and dual cores is expected to be released soon, which should be quite an interesting chip. It's kind of a pity that it's held back by being a Freescale chip
The other annoying issue is latency, which is the amount of time it takes between the processor starting a memory read, and the first bit of the data reaching it. The G5's bus is rather high latency, which hurts it on certain types of code. Presumably it's designed with a bandwidth-uber-alles approach that sacrifices latency in places, but I don't really know.
