If I understand it correctly, DDR5 has ECC included by default.
Yes and no.
"...All the while, there are several smaller changes to either support these goals or to simplify certain aspects of the ecosystem, such as on-DIMM voltage regulators as well as on-die ECC. ..."
www.anandtech.com
"...On-die error correction code (ECC)3 and error check and scrub (ECS), which were first to be adopted in DDR5, also allow for more reliable technology node scaling by correcting single bit errors internally. Therefore, it is expected to contribute to further cost reduction in the future. ECS records the DRAM defects and provides the error counts to the host, thereby increasing transparency and enhancing the reliability, availability, and serviceability (RAS) function of the server system. ..."
https://news.skhynix.com/why-ddr5-is-the-industrys-powerful-next-gen-memory/
This falls into the same "slim shady' zone as to why Apple punts on doing user data ECC checking in APFS. They may skip implementing it for the same "less work for us to do a half implementation" reasons. There is ECC as long as the data is on the die ( not even the chip or DIMM ; probably going to get die stacking in the chips within numerous Apple system implementations ). If the flaw occurs during the transition from the RAM die to the CPU then, no they don't.
There is still an optionally wider data path ( 80 bits instead of 64 ) so there will still be ECC and non-ECC DIMMs with DDR5 where the data path also has optional pragmatic coverage.
Apple hand waves that APFS doesn't need ECC on user data because the storage drive has ECC. ( in particular their SSD which is the nominal default place to store data in its encrypted state. ). That's likely to "happen to work" fairly well to average data movement. If you have long term bit critical data, then it is substantially less than what something like ZFS or some other alternatives offer (end to end coverage). Power loss protection on their SSDs in plug-in desktops... not really.
I would be completely unsurprised if Apple rolls out the same exact hand waving about why they didn't have to put in the work for their top end "Pro" SoC. "It is protected most of the time... that's good enough for iPhones so it is good enough for us. "
LPDDR5 seems to have it optional, but I have no idea if it’s actually used anywhere. Anyway, given the increasing speed and density of RAM, ECC will quickly become a must.
16 less pins (and traces ) per DIMM over 4-8 DIMMs is decent amount of avoided work that many system implementors are going to avoid to scrape out incrementally better margins. More of the basic ECC infrastructure is a ubiquitous basic cost so hopefully it will get more widespread. At least in the mid range systems. The stuff at the lower end of the "race to the bottom" will probably still skimp.