MP 7,1 MP7,1 16-core's specified processor cache - L1 32k/32k x16 and L2/L3 Cache 38MB

[bxs]

Subject: MP7,1 16-core's specified processor cache - L1 32k/32k x16 and L2/L3 Cache 38MB

The processor cache specs were obtained from Apple's web site (L3 38MB) and the EveryMac.com web site - https://everymac.com/systems/apple/...on-w-silver-tower-workstation-2019-specs.html which states L1 32k/32k x16 and L2/L3 Cache 38MB.

Questions:

1. Is the L3 Cache shared among the cores allowing for fast inter-core communication ?
2. Is the L2 Cache 38MB in size and is it shared among the cores?
3. If L3 cache is 38MB does this mean each core has 38MB to itself or only a portion of it if L3 shared as asked in 1).
4. If every core and every hyper thread (a total of 32) are in full swing and accessing memory how is the processor's cache allocated to these 32 execution threads?

Thanks....

 

[arock]

L2 cache is 1MB per core. L3 cache is 22MB. Total is 22MB + (1MB * 16) = 38MB. L3 cache is shared by all threads, L2 cache is dedicated to the core it is assigned to and the hyperthread for that core.

 

[bxs]

L2 cache is 1MB per core. L3 cache is 22MB. Total is 22MB + (1MB * 16) = 38MB. L3 cache is shared by all threads, L2 cache is dedicated to the core it is assigned to and the hyperthread for that core.

Thank you. 👍
BTW, where did you obtain that information ?

 

[arock]

The L3 info is specified on Intel's website. I must have read the L2 details somewhere else, as I can't find them on this Intel webpage: https://ark.intel.com/content/www/u...xeon-w-3245-processor-22m-cache-3-20-ghz.html

EDIT: Here's more detail including L2 organization on Wikichip:

Xeon W-3245 - Intel - WikiChip

W-3245 is a 64-bit hexadeca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3245 operates at 3.2 GHz with a TDP of 205 W, a turbo boost frequency...

en.wikichip.org