....
Unclear though: are the PCIe connectors the same? I doubt it, as I suspect the 2nd GPU w SSD actually contains 2 PCIe "connectors" (i.e. lanes) either that or it uses a switch or some other hack (maybe 8 lanes to GPU and 4 to PCIe flash instead of 16 to GPU) to split things out.
This image is suspected to come from a service manual.
http://i.imgur.com/ItIqxDY.png
Anandtech's probing produced a similar mapping
http://www.anandtech.com/show/7603/mac-pro-review-late-2013/8
[ The difference is largely the placement of the discrete USB 3.0 controller. And Aantech's math on the switch is correct. Not sure what bandwidth a USB 3.0 controller is getting if fully load all three TB controllers. connecting to PCH avoids that problem. ]
The problem is there are no substantive PCIe lanes (and bandwidth) for a second SSD to connect to. Apple loads all of the display load onto one GPU (so harder to "short change" it on bandwidth) and trimming bandwidth off of a compute GPGPU generally makes even less sense if looking to provide top performance.
The PCH/chipset is max out. Even if they could choke off and de-duplicate Ethernet and squeeze in a x2 PCIe SSD (from MBPs) but it would lower bandwidth than the other one. ( PCH typically goes 4 x1 + 1 x4 or 8 x1 ).
What Apple needs is either a PCH/chipset that has more PCIe v2 lanes (4 more ) or has eight v3 lanes In the first case, for the Mac Pro the SATA lanes the PCH provides are useless and the USB lanes are largely same way. Apple (and others ) may convince Intel they need another variant in their chipset line-up. In the second case, some of those eight lanes can be split ( x4 PCIe v3 switched into two x4 PCIe v2 lanes bundles ) and/or the SSDs upgraded to PCIe v3 so demand less lanes ( just x2 SSDs ) .
The next generation PCH chipset ( 610 series ) has USB 3.0. If believe the diagram then could propose to tap the "extra" x4 on the I/O board switch when the discrete USB 3.0 controller gets absorbed. Looks like a couple of potential problems there both short and long term.
A. hugely unequal trace lengths. The TB controllers are co-located with switch while the SSD line would have to bounce down to backplane and up to card.
B. Apple may punt for a long time on USB 3.1 but that's another multi lane consumer coming down the pike.
C. Thunderbolt is potentially going to blow past the total PCIe v3 budget also if it switches to the newer bandwidth.