RISC-V is coming... near future.

[sunny5]

Apple Possibly Exploring Open-Source Alternative to Arm Architecture

Apple may be exploring the possibility of using an open-source alternative to the Arm architecture, which it's been using in its products for...

www.macrumors.com

It seems Apple is investing on RISC-V development for their uses. Yes, RISC-V is better than ARM in many ways but if they really gonna use it, how about the compatibility? We might need to expect another huge transition just like x86 to ARM. I dont know if ARM is compatible with RISC-V without problems or not. But using RISC-V might be a future cause the power consumption is 60% lower and the chip size is 30~50% smaller than ARM and yet, it can reach 5ghz for only 1W. For now, they might replace some controllers with RISC-V which doesn't affect the compatibility issue.

I dont know anything about RISC-V and if Apple can use it for future Apple Silicon without a compatibility issue, then I'm in but kinda doubtful.

Thoughts?

 

[Jorbanead]

Seems like they’re just exploring options here, and if they were to do some sort of major transition it wouldn’t be for another 10-15 years anyways. A company like Apple has teams of people exploring all kinds of hardware, software and other things that may never come to fruition.

 

[CWallace]

In the end, it will depend on how RISC-V balances against ARM in terms of power consumption and performance. If RISC-V proves superior, then I expect Apple will start to consider switching. If not, then I expect Apple will continue to stick with ARM.

If Apple does decide to switch, I would not be surprised if (even if I do not necessarily expect) we will see the entire product line go over in one move because everything is now on ARM so the underlying OSes all leverage ARM.

 

[leman]

But using RISC-V might be a future cause the power consumption is 60% lower and the chip size is 30~50% smaller than ARM and yet, it can reach 5ghz for only 1W. For now, they might replace some controllers with RISC-V which doesn't affect the compatibility issue.

This is complete nonsense. The practical difference between RISC-V and ARM is minuscule. If anything, RISC-V needs more instructions to encode the same algorithm. How would two almost equivalent ISAs create such a big difference? Your claims of lower power consumptions come from a single test using a noninformative microbenchmark with a CPU that is an unknown quantity.

 

[sunny5]

This is complete nonsense. The practical difference between RISC-V and ARM is minuscule. If anything, RISC-V needs more instructions to encode the same algorithm. How would two almost equivalent ISAs create such a big difference? Your claims of lower power consumptions come from a single test using a noninformative microbenchmark with a CPU that is an unknown quantity.

Proof?

 

[leman]

Proof?

What proof? Shouldn’t you be the one providing proof for your outlandish claims?

 

[ADGrant]

In the end, it will depend on how RISC-V balances against ARM in terms of power consumption and performance. If RISC-V proves superior, then I expect Apple will start to consider switching. If not, then I expect Apple will continue to stick with ARM.

If Apple does decide to switch, I would not be surprised if (even if I do not necessarily expect) we will see the entire product line go over in one move because everything is now on ARM so the underlying OSes all leverage ARM.

I am sure the Apple chip designers can make either instruction set work well. The real advantage of RISC-V over ARM is cost. Apple pays a license fee to ARM to use their instruction set in Apple Silicon. RISC-V is open source.

 

[sunny5]

What proof? Shouldn’t you be the one providing proof for your outlandish claims?

First, you said ARM and RISC-V's difference is minuscule and yet you didnt provide any info.

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W | bit-tech.net

And it claims that its design could implement 25 physical cores in a 5W TDP budget.

bit-tech.net

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W.

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in...

www.hpcwire.com

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim...

www.hpcwire.com

1000~4000 cores with RISC-V is in development which both x86 and ARM cant do. The power consumption is extremely low too.

Yes, those are prototypes but it's already beat both ARM and x86 so real products might be better than those.

 

[leman]

First, you said ARM and RISC-V's difference is minuscule and yet you didnt provide any info.

RISC-V ISA is open source, go read through the documentation. ARM ISA documentation is also freely available. What kind of info do you expect me to provide? These are all matters of public record. And yes, I’ve read most of them.

Code density and instruction count comparisons:

https://project-archive.inf.ed.ac.uk/ug4/20191424/ug4_proj.pdf

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W | bit-tech.net

And it claims that its design could implement 25 physical cores in a 5W TDP budget.

bit-tech.net

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W.

Show me some industry standard benchmarks. SPEC, even Geekbench or some browser benchmarks will do. I don’t know what CoreBench does. From the developers description, it only measures low-level ALU performance. This has nothing to do with running real-world code. Furthermore, we have zero information about that CPU. It could be something very simple designed to run at high frequencies abs low power consumption, but sacrificing everything that actually makes CPUs go fast (out of order execution, branch prediction, caching).

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in...

www.hpcwire.com

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim...

www.hpcwire.com

1000~4000 cores with RISC-V is in development which both x86 and ARM cant do. The power consumption is extremely low too.

These are specialized ML units. It has nothing to do with running general purpose code. These cores are extremely simple and hence energy efficient. You could also be arguing that a two-stroke diesel engine is more efficient than a modern fuel injection car engine since it’s what ships use abs they can transport more cargo per unit of fuel used. You have to take the context into account.

 

[sunny5]

RISC-V ISA is open source, go read through the documentation. ARM ISA documentation is also freely available. What kind of info do you expect me to provide? These are all matters of public record. And yes, I’ve read most of them.

Code density and instruction count comparisons:

https://project-archive.inf.ed.ac.uk/ug4/20191424/ug4_proj.pdf

You want me to read to find that ARM and RISC-V are similar? Wow, I guess you really dont wanna prove your point.

Show me some industry standard benchmarks. SPEC, even Geekbench or some browser benchmarks will do. I don’t know what CoreBench does. From the developers description, it only measures low-level ALU performance. This has nothing to do with running real-world code. Furthermore, we have zero information about that CPU. It could be something very simple designed to run at high frequencies abs low power consumption, but sacrificing everything that actually makes CPUs go fast (out of order execution, branch prediction, caching).

These are specialized ML units. It has nothing to do with running general purpose code. These cores are extremely simple and hence energy efficient. You could also be arguing that a two-stroke diesel engine is more efficient than a modern fuel injection car engine since it’s what ships use abs they can transport more cargo per unit of fuel used. You have to take the context into account.

RISC-V is only 10 years old for development and yet you are expecting too much. Those info I provided is enough and they are advancing with RISC-V annually. Infos that I mentioned came from the early stage of RISC-V and WD and some companies already using it.

 

[Jorbanead]

First, you said ARM and RISC-V's difference is minuscule and yet you didnt provide any info.

The burden of proof is always on the one who made the first claim. Leman doesn't have to prove any point until you can adequately defend yours, which Leman is saying you have not done yet. AFAIK Leman has a background in development and knows, to my knowledge, a decent amount of information when it comes to this type of stuff.

Not sure what your qualifications are though if you'd want to share? Be careful with that laugh react button, you may break it one of these days.

 

[sunny5]

The burden of proof is always on the one who made the first claim. Leman doesn't have to prove any point until you can adequately defend yours, which Leman is saying you have not done yet. AFAIK Leman has a background in development and knows, to my knowledge, a decent amount of information when it comes to this type of stuff.

Not sure what your qualifications are though if you'd want to share? Be careful with that laugh react button, you may break it one of these days.

And there isn't any proof that ARM and RISC-V's differences are minuscule which he failed to prove it. Being a developer doesn't prove anything also.

 

[Jorbanead]

And there isn't any proof that ARM and RISC-V's differences are minuscule which he failed to prove it. Being a developer doesn't prove anything also.

Ignoring my whole point about burden of proof. You made the original claim so rather than deflecting, you could just support your arguments and provide some sort of qualification.

 

[cmaier]

Apple Possibly Exploring Open-Source Alternative to Arm Architecture

Apple may be exploring the possibility of using an open-source alternative to the Arm architecture, which it's been using in its products for...

www.macrumors.com

It seems Apple is investing on RISC-V development for their uses. Yes, RISC-V is better than ARM in many ways but if they really gonna use it, how about the compatibility? We might need to expect another huge transition just like x86 to ARM. I dont know if ARM is compatible with RISC-V without problems or not. But using RISC-V might be a future cause the power consumption is 60% lower and the chip size is 30~50% smaller than ARM and yet, it can reach 5ghz for only 1W. For now, they might replace some controllers with RISC-V which doesn't affect the compatibility issue.

I dont know anything about RISC-V and if Apple can use it for future Apple Silicon without a compatibility issue, then I'm in but kinda doubtful.

Thoughts?

RISC-V isn’t better than Arm in any ways I can think of. It is not smaller nor more power efficient. (The chips that have come out are smaller and more power efficient only because they are not aiming at equal performance. If Apple wanted to make a ****** Arm chip, it could easily make one with the same performance and power consumption and die size as whatever the best RISC-V is.)

 

[cmaier]

And there isn't any proof that ARM and RISC-V's differences are minuscule which he failed to prove it. Being a developer doesn't prove anything also.

How about being a CPU designer?

In fact, RISC-V has several disadvantages. It’s little-endian (Arm allows both big- and little-end Ian). It’s a very small instruction set (which means you need more instructions, which complicates the instruction fetch/cache hardware). To make code size reasonable, you have to use 16-bit RVC substitutes, which causes even more problems.

I’m not saying Arm is better for every purpose, but there’s certainly nothing in RISC-V that makes it better than Arm for any purpose I can think of, other than avoiding licensing fees (which Apple probably doesn’t pay anyway, or which are at least very very cheap for Apple).

 

[thekev]

First, you said ARM and RISC-V's difference is minuscule and yet you didnt provide any info.

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W | bit-tech.net

And it claims that its design could implement 25 physical cores in a 5W TDP budget.

bit-tech.net

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W.

No one cares about GHz on their own. They measure clock speed, which is a poor indicator of performance, given the prevalence of superscalar pipelines and dynamically clocked chips. You can only reason about GHz if all other aspects of a processor design are held constant. Also, your initial post referred to RISC-V, which is an instruction set architecture. An ISA does not have wattage or clock speed.

 

[Gerdi]

First, you said ARM and RISC-V's difference is minuscule and yet you didnt provide any info.

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W | bit-tech.net

And it claims that its design could implement 25 physical cores in a 5W TDP budget.

bit-tech.net

Micro Magic 64-bit RISC-V CPU runs at 5GHz on 1W.

Yes, those are prototypes but it's already beat both ARM and x86 so real products might be better than those.

The numbers quoted for the M1 by Micro Magic are totally fictional and the presented calculation is utter nonsense. And referring to the Cortex A9 as the fastest ARM core is ... at least very misleading - it was used in phones like 10 years ago or so.
I wonder why they are claiming such obvious nonsense? Well perhaps because it is not obvious for everyone, like SunnyS?

 

[leman]

You want me to read to find that ARM and RISC-V are similar? Wow, I guess you really dont wanna prove your point.

You are a really funny one. By your own admission, you don’t have any clue about ARM or RISC-V, and you are also not interested in learning about them. Yet you are arrogant enough to make claims which of these architectures is supposed to be more energy efficient.

If you want to discuss the merits of different instruction sets you first have to spend some time trying to understand them.

RISC-V is only 10 years old for development and yet you are expecting too much. Those info I provided is enough and they are advancing with RISC-V annually. Infos that I mentioned came from the early stage of RISC-V and WD and some companies already using it.

Well, ARM64 is also only 10 years old. And yet it has a rich instruction set (including various kind of SIMD support, virtualization and security) and some of the fastest CPUs ever built are ARM64. Over these 10 years it has made much more progress than RISC-V because it actually has commercial support and a lot of focused R&D momentum whereas RISC-V has mostly been a committee-led academic research platform centered around microcontrollers and specialized chips. RISC-V does not have stable SIMD, bit manipulation or hypervisor support - basic everyday features of personal computing. It is simply not ready for general purpose high performance computing. It’s a great little core architecture that allows companies to develop small specialized chips that don’t need too many features without paying high license fees, and it definitely has future potential, but it’s not nearly ready to challenge ARM64. And even then it won’t offer any notable advantages except being free.

P.S. here is an insightful criticism of RISC-V by someone infinitely more knowledgeable than me. It’s a biased source (the author is a CPU designer who used to work for ARM), but IMO they make a great job of delivering their points in a compact and objective way. You can use it as a starting point to learn about particularities of RISC-V design: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68

 

[ADGrant]

Well, ARM64 is also only 10 years old. And yet it has a rich instruction set (including various kind of SIMD support, virtualization and security) and some of the fastest CPUs ever built are ARM64. Over these 10 years it has made much more progress than RISC-V because it actually has commercial support and a lot of focused R&D momentum whereas RISC-V has mostly been a committee-led academic research platform centered around microcontrollers and specialized chips. RISC-V does not have stable SIMD, bit manipulation or hypervisor support - basic everyday features of personal computing. It is simply not ready for general purpose high performance computing. It’s a great little core architecture that allows companies to develop small specialized chips that don’t need too many features without paying high license fees, and it definitely has future potential, but it’s not nearly ready to challenge ARM64. And even then it won’t offer any notable advantages except being free.

P.S. here is an insightful criticism of RISC-V by someone infinitely more knowledgeable than me. It’s a biased source (the author is a CPU designer who used to work for ARM), but IMO they make a great job of delivering their points in a compact and objective way. You can use it as a starting point to learn about particularities of RISC-V design: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68

Thanks for the link, very interesting. The lack of hypervisor support eliminates the possibility of using the RISC-V architecture as a server platform.

The other major disadvantage for RISC-V is the mature compiler support available for the ARM architecture. ARM CPUs have been used in mobile devices since the early 90s and the developers of the GCC, Clang and even Microsoft C++ compilers have had a lot of time to work on compiler optimizations.