SRAM density improvement with N2

[hoodlum90]

When we went from N5 to N3 there was no improvement in SRAM density. There was some question on whether we had hit a wall with SRAM. TSMC will be presenting a paper in December where this is one of the items that will be discussed, and it looks like we will have an ~20% increase in SRAM density.

SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements

SRAM scales again with GAA transistors.

www.tomshardware.com

But a noteworthy aspect of TSMC's N2 is that this production node also shrinks HD SRAM bit cell size to around 0.0175 µm^2 (enabling SRAM density of 38 Mb/mm^2), down from 0.021 µm^2 in the case of N3 and N5, according to a paper that TSMC will present at the upcoming IEDM conference this December.

 

[Gnattu]

Combine this with the M5 starting to use SoIC packaging rumors: https://www.macrumors.com/2024/07/04/apple-m5-chips-advanced-packaging-tsmc/ it would be quite interesting to see what we will get for M5 and M6. We could see something with AMD X3D like packaging in future Apple Silicon.

 

[Pressure]

Combine this with the M5 starting to use SoIC packaging rumors: https://www.macrumors.com/2024/07/04/apple-m5-chips-advanced-packaging-tsmc/ it would be quite interesting to see what we will get for M5 and M6. We could see something with AMD X3D like packaging in future Apple Silicon.

The M3 Max already has a hefty 48MB of System-Level Cache besides large 192+128 KiB L1 per core and 32MB L2 cache on die.

For comparison the Zen5 only has 80+48KiB L1 per core, 1MB L2 and 32MB L3 cache (plus the optional under-die 64MB of 3D V-Cache).

It might be too slow for Apple Silicon compared to the current solution but it will free up a lot of transistors on the SoC.

Just taking the SRAM improvement from N2 and scale it up by 20% would leave Apple Silicon at 96MB combined SLC and L2 cache (which will be much faster to access than the 96MB L3+3D V-Cache of Zen5).

Apple Silicon already has industry-leading deep out-of-order reorder buffer registers (ROBs) as well.

 

[altaic]

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