1,000 is not "volume" production. TSMC produces 120k+ 5nm wafers each month.
1,000 is simply risk production.
Hard to tell. If Intel 'bailed' on Q4 and Apple was only targeting very low volume , very expensive then 1,000 is relatively high volume. Even 100/month is higher than zero/month. When a major wafer start reservatin flakes to zero then opens up bubbles in the pipeline. ( and causes ripples down stream).
This is somewhat consistent with the reports about a year or so ago where Intel had bought up the large bulk of the N3 capacity. Probably nn the first couple of quarters of the N3 ramp. Apple's large volume was/is on N5P so Apple was only doing relatively low volume stuff so Intel's wafer starts would dwarf Apple's at the start.
Intel was only making a iGPU tile ( not a whole processor just the GPU and perhaps some of the memory controller part). That tile probably would be in half the size of an A-series process ( Ax ~ 90mm2 so perhaps around ~45mm2 ). 2-3 thousand of what is now idle wafer starts would be been more than enough to generate a heathy amount to be coupled to larger and more numerous Intel tile/chiplets. If Intel had gone "expensive to end user iGPU" first even more so.
The number of wafers in flight has very little to do whether have crossed the 'at risk' to 'high volume manufacturing' (HVM) threshold. That threshold is far more about has the defect level dropped down to where ramping volume generally makes sense or not. Technically, it is another dimension if customers are pushing through orders or not. Usually customers are chomping at the bit to turn the wafer order spigot on at the HVM so they tend to coincide but there are not the same thing.
Apple really doesn't need very high volume N3. The 'plain' M2 doesn't need it desperately. A16 probably doesn't need it (either yet another N5P bloat or N4/N4P. N3 is way, way too late for A16 on the years ago roadmaps plans. ). M2 Pro may not even need it. ( to get a M2 Pro Mini out the door in late 2022 to wrap up the Mini transition).
Intel is in chip stepping revision hole on their GPUs. Arc Alchemist having even completed the gen 1 roll out yet (even if Intel did have a completed discrete GPU on N3 queued up to soak up extra N3 wafer volume. ) . Intel's schedule would have had to be almost perfect for the N3 iGPU tile to roll out in very late Q4 '22. I suspect that was a hedge in case Gen 13 (Raptor Lake sucked really bad). Turns out it is the iGPU that has problems and Gen 13 (for it is) is the relatively low problematical SoC. Intel doesn't need to prematurely retire Gen early in 1H 2023.
If the Intel + Apple bidding war on early N3 wafer starts squeezed everyone else out in Q4 '22 then the other folks would have planned their logistics for Q1-Q3 '23. Pulling high volume dies backward in release times is not easy. These chips go into packages/systems with other chips. There are lots of pieces that also would need to be pulled backward also. It is usually much easier to slide the systems to a forward on the time line to work out a logistics issue.
Expectations are that TSMC will start mass production of 3nm in Q4 2022. This 1,000 report is either wrong or TSMC isn't starting mass production yet in Q4 2022.
Or TMSC's customer(s) screwed up also. Decent chance Intel may be have to pay a sizable penalty if this is a very high wafer start 'flake' that opened a hole.
It isn't like TSMC can't shift some of the ASML systems over to doing N4P, N4 work. There are other customers who likely wafer start constrained on something older than N3 that TSMC can use a subset of the systems for. There are tools that are likely N3 specific that will be idled but there are other tools that span past N3 in utility.
www.techpowerup.com
ctee.com.tw
