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bxs

macrumors 65816
Original poster
Oct 20, 2007
1,180
553
Seattle, WA
I'm interested in knowing how the Processor hardware embedded Vector instruction set improves the FLOPS number from the Apple's claimed number on their iMP web page ?

I suspect Geekbench 4 does not, at this time, have its code recompiled to employ the vector instructions and therefore will only show/display Apple's FLOPS claim.

I guess I can write a simple program to exploit the new vector instructions and have it report the FLOPS to compare against what Geekbench 4 reports.

Thoughts.... ?
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https://www.geekbench.com/doc/geekbench4-cpu-workloads.pdf

Floating Point Workloads GEMM

GEMM (General Matrix Multiplication) computes the result C = AB + C, where A, B, and C are matrices.

The GEMM workload uses 512x512 single-precision matrices. The GEMM implementations are written using hand-tuned vector instructions for the following instruction sets:

• AVX + FMA
• AVX
• SSE3
• SSE2

• ARMv8 NEON • ARMv7 NEON

so-- I think that this is already incorporated. see https://www.intel.com/content/www/us/en/architecture-and-technology/avx-512-overview.html

With ultra-wide 512-bit vector operations capabilities, Intel® AVX-512 can handle your most demanding computational tasks.

Applications can pack 32 double precision and 64 single precision floating point operations per second per clock cycle within the 512-bit vectors, as well as eight 64-bit and sixteen 32-bit integers, with up to two 512-bit fused-multiply add (FMA) units, thus doubling the width of data registers, doubling the number of registers, and, doubling the width of FMA units, compared to Intel® Advanced Vector Extensions 2.0 (Intel® AVX2).3

Is there an anomalously high GEMM sub-score among cpus that support avx-512?
 
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