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Ulfric

macrumors regular
Original poster
Apr 4, 2018
160
124
First patent is about GPU chiplets using high bandwidth crosslink.


Patent link
GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS - ADVANCED MICRO DEVICES, INC. (freepatentsonline.com)

Another one is a Programmable Execution Unit (PEU) allows Customizable Instructions and Adaptable Computing.

Patent link
METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE INSTRUCTIONS IN COMPUTER SYSTEMS - Advanced Micro Devices, Inc. (freepatentsonline.com)

Here are some highlights of the patent:

  • Processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions
  • When a processor loads a program, it also loads a bitfile associated with the program which programs the PEU to execute the customized instruction
  • Decode and dispatch unit of the CPU dispatches the specialized instructions to the PEUs
  • PEU shares registers with the FP and Int EUs.
  • PEU can accelerate Int or FP workloads as well if speedup is desired
  • PEU can be virtualized while still using system security features
  • Each PEU can be programmed differently from other PEUs in the system
  • PEUs can operate on data formats that are not typical FP32/FP64 (e.g. Bfloat16, FP16, Sparse FP16, whatever else they want to come up with) to accelerate machine learning, without needing to wait for new silicon to be made to process those data types.
  • PEUs can be reprogrammed on-the-fly (during runtime)
  • PEUs can be tuned to maximize performance based on the workload
  • PEUs can massively increase IPC by doing more complex work in a single cycle

Even though I am saying on die FPGA, tt's not a normal on-die FPGA. They usuallyy sit at about the same distance as L3 cache and transfers between the CPU cores and the FPGA take ages.

This patent is directly integrating small FPGAs as execution units of each cpu core
 
Last edited:
First patent is about GPU chiplets using high bandwidth crosslink.


Patent link
GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS - ADVANCED MICRO DEVICES, INC. (freepatentsonline.com)

Another one is a Programmable Execution Unit (PEU) allows Customizable Instructions and Adaptable Computing.

Patent link
METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE INSTRUCTIONS IN COMPUTER SYSTEMS - Advanced Micro Devices, Inc. (freepatentsonline.com)

Here are some highlights of the patent:

  • Processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions
  • When a processor loads a program, it also loads a bitfile associated with the program which programs the PEU to execute the customized instruction
  • Decode and dispatch unit of the CPU dispatches the specialized instructions to the PEUs
  • PEU shares registers with the FP and Int EUs.
  • PEU can accelerate Int or FP workloads as well if speedup is desired
  • PEU can be virtualized while still using system security features
  • Each PEU can be programmed differently from other PEUs in the system
  • PEUs can operate on data formats that are not typical FP32/FP64 (e.g. Bfloat16, FP16, Sparse FP16, whatever else they want to come up with) to accelerate machine learning, without needing to wait for new silicon to be made to process those data types.
  • PEUs can be reprogrammed on-the-fly (during runtime)
  • PEUs can be tuned to maximize performance based on the workload
  • PEUs can massively increase IPC by doing more complex work in a single cycle

Even though I am saying on die FPGA, tt's not a normal on-die FPGA. They usuallyy sit at about the same distance as L3 cache and transfers between the CPU cores and the FPGA take ages.

This patent is directly integrating small FPGAs as execution units of each cpu core
Neither of these is a patent
 
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Neither of these is a patent
Patent Application? Now are you happy? Couldn't use the entire term because of shortage of space on the headline. I suppose you haven't come here to nitpick on such trivial issue.
 
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