14th November Possible New Release Date?

[Neodym]

Xeon 51xx (B2 only)

Xeon 51xx had another stepping ("G0").

 

[nanofrog]

Xeon 51xx had another stepping ("G0").

Missed that one (only recalled G0 with 53xx series).

Double checked the 50xx series though (both ark.intel.com and cpu-world.com, and the other steppings were pre-production ES/QS parts).

 

[Tutor]

Does anyone know of decent articles with "reasonable" assumptions of how Ivy bridge consumer CPUs will compare to Sandy Bridge E?

Can't vouch for reliability, but this is what Wikipedia says (http://en.wikipedia.org/wiki/Sandy_Bridge ):

Performance

Sandy Bridge - Up to 17% more CPU performance clock-for-clock compared to Lynnfield processors.
Around twice the integrated graphics performance compared to Clarkdale's (12 EUs comparison).

Ivy Bridge - Intel's performance targets (compared to Sandy Bridge)
20% increase in CPU performance.
Up to 60% increase in integrated graphics performance.

 

[deconstruct60]

I realize this, but what has me concerned, is the number of steppings this close to the release of the SP consumer parts (will initially release with C1 from what I recall from another article).

Actually it is C1

http://ark.intel.com/products/63696...Extreme-Edition-(15M-Cache-3_30-GHz)#ordering

So the softpedia article is wrong ( It says "C2" ). Which puts into doubt their C3 labeling as well.

Furthermore the 3960X entry says that VT-d is working. Isn't that what one of these "future" steppings was suppose to fix? If it was broken why wouldn't Intel just turn that checkbox to "off" and disable?

I'm not sure if they'll hold off until the die shrink for D steppings (would like to see more on the errata specifics with C3 and later).

isn't the die shrink called "Ivy Bridge" ?

Xeon 50xx (C1 only)

Which was the dead-end NetBurst architecture. Dead ender means likely no steppings. That shouldn't be particularly surprising. So OK, refined to "always do stepping for architectures still on evolutionary path".

The motivation to fix the bugs is that often functionality is copied or tweaked in the next generation designs. If there is a fundamentally flawed design choice present you'd want to identify and find the root cause so as to stop the propagation. Additionally, since these processors will sell over multiple year product lifetimes there is amble time to fix the product and recover the incremental cost in both the current and future lines.

 

[nanofrog]

Actually it is C1

http://ark.intel.com/products/63696...Extreme-Edition-(15M-Cache-3_30-GHz)#ordering

So the softpedia article is wrong ( It says "C2" ). Which puts into doubt their C3 labeling as well.

It seems VR-zone was the original source of this (here).

Perhaps the article is wrong (as are all subsequent articles that trace back to the VR-zone article as it's source), but it may also be Intel pulling a technicality of sorts (i.e. claims that the board doesn't support it).

Digging into the errat might reveal something (if there is indeed an issue), or prove that the original article is wrong.

Which was the dead-end NetBurst architecture. Dead ender means likely no steppings. That shouldn't be particularly surprising. So OK, refined to "always do stepping for architectures still on evolutionary path".

You asked a question, and I posted proof that it has actually happened (no further specifications).

But the point was, that previous Xeons haven't had that many steppings with production parts (typically has been 2 with the various 5xxx parts from what I recall).

Now if the articles are incorrect as to the stepping information, then LGA2011 may not have that many stepping revisions. But given recent corporate trends to use omission to their advantage, there could be more to it than just a simple Yes/No as to VT-d = 100% in a board that supports it (parts and microcode comply).