You mean EP? Socket 1356 is the replacement for 1366. Since the Mac Pro is on 1366 now, its seems only reasonable that it will go to 1356. Therefore it should be EN, not EP.
No it is not reasonable. The E5 Xeon place the PCI-e controller
inside the CPU package. The '-EN' series looses PCI-e lanes from what it could have ( among some other things. ). Additionally, it is going to arrive later.
There are "uniprocessor" versions of the E5 ( 1600 ) that fit the 2011 socket (socket R)
http://www.cpu-world.com/news_2011/2011020803_Details_on_Intel_Xeon_E5_product_families.html
If Apple selected the some 1600 versions (replacement for the 3500 & 3600 series in current ) and 2600 ( replace for the 5600 series in current) that would be the natural line up.
The only reason to slide updates to 2012 to wait for the 2400 series would be that the prices on the 1600 and 2600 didn't closely match those of the (3500 & 3600) and 5600 options. Instead of '3' and '5' it is '1' and '2' as leading prefixes. Otherwise, it is a loosing choice because the 2400 series has the following properties:
i. it comes out much later.
ii. fewer high speed PCI-e lanes. (*)
iii. Mismatch to the 4 DIMM slot design. (**)
iv. lower memory bandwith because still stuck at 3 memory controllers when have increased cores and internal throughput. ( lower top end throughput on heavy workloads).
I think the 2400 Xeon is aimed at sub $2,000 "mini-tower" workstations and sub $1,500 servers. Systems where shaving costs to keep the price down. However, so is the 1600 and it comes out sooner. [guessing but suspect the 1600's will have higher clock rate and the 2400's will be slower but allow for dual packages with mild bandwidth problems (only QPI link for both processor and southbridge traffic) in similar system price zones. )
* -- Apple could "get by" with fewer lanes since only going to have around 4 slots. However, current designs use a switch. It would be better to get rid of the switch. 4 slots with 100% throughput.
** -- if Apple sticks with the horizontal daughtercard design for the CPU/Memory sockets then 4 is all have room for unless case gets a bump in width. While Apple probably won't go multiple DIMMs per channel ( 2400 shaves the limit to cut costs). Peak memory bandwidth is better if go 'wide' ( as opposed to 'deep' )