...and 8 PCIe 2.0 lanes from the C600 PCH.
Perfect match - T-Bolt 2 is PCIe 2.0 x4 .
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2016 nMP
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...and 8 PCIe 2.0 lanes from the C600 PCH.
Perfect match - T-Bolt 2 is PCIe 2.0 x4 .
Lets clean some things: Nvidia will show on GTC Pascal. We can expect 3 types of memory for those chips: Low end - GDDR5, mid - end GDDR5X, and High-End/HPC - HBM2. The problem is that 8 GB chips are not in production yet. So the GPUs using them will appear later in the year.
Other thing are HBM2 4GB chips... They are in Mass production already. Each stack brings 256 GB/s with possibility of making 16 GB GPU made from them, accounting for 1 TB/s of Bandwidth. So Early Pascal GPU with HBM2 is possible, regardless of what I have written before. Just with 16 GB of VRAM. The question is: where it will be seen. My opinion is that first it will appear in HPC market, later on consumer. Will Apple use them for next gen Mac Pro? It depends how much Nvidia will charge for them. But IMO: highly unlikely. GDDR5X. Mass production starting in the summer, it will go to GTX980/970 successors. We have to account 2-3 months before mass availability, so we are looking at late Q3, as well.
About Polaris. Well, before I claimed that both of Polaris GPUs will use GDDR5. Now tho, I am not so sure. I think there is quite big chance that Polaris 11 will use HBM2, 2 stacks of 2 GB accounting for 512 GB/s. It will reduce the memory controller area on die to minimum, and increase the shader count on the GPU. All of this: just 2 stacks of HBM2, will bring possibility of bringing HBM lower into the segment. Also AMD will be able to charge more at the start for lets say: 4096 GCN4 core GPU with 4 GB of VRAM, and it will not be impossible to make the stacks 4 GB, bringing 8 GB of VRAM. Of course with higher price point. Or selling them as semi custom versions, to OEMs that would require them. Of course, I am only guessing here... But again, if 2-3 months are needed for getting HBM2 onto market we again are looking at march-april release dates. Q2-Mid of the Year, as has been said by AMD officials.
Other thing are HBM2 4GB chips... They are in Mass production already. Each stack brings 256 GB/s with possibility of making 16 GB GPU made from them, accounting for 1 TB/s of Bandwidth. So Early Pascal GPU with HBM2 is possible, regardless of what I have written before. Just with 16 GB of VRAM. The question is: where it will be seen. My opinion is that first it will appear in HPC market, later on consumer. Will Apple use them for next gen Mac Pro? It depends how much Nvidia will charge for them. But IMO: highly unlikely. GDDR5X. Mass production starting in the summer, it will go to GTX980/970 successors. We have to account 2-3 months before mass availability, so we are looking at late Q3, as well.
About Polaris. Well, before I claimed that both of Polaris GPUs will use GDDR5. Now tho, I am not so sure. I think there is quite big chance that Polaris 11 will use HBM2, 2 stacks of 2 GB accounting for 512 GB/s. It will reduce the memory controller area on die to minimum, and increase the shader count on the GPU. All of this: just 2 stacks of HBM2, will bring possibility of bringing HBM lower into the segment. Also AMD will be able to charge more at the start for lets say: 4096 GCN4 core GPU with 4 GB of VRAM, and it will not be impossible to make the stacks 4 GB, bringing 8 GB of VRAM. Of course with higher price point. Or selling them as semi custom versions, to OEMs that would require them. Of course, I am only guessing here... But again, if 2-3 months are needed for getting HBM2 onto market we again are looking at march-april release dates. Q2-Mid of the Year, as has been said by AMD officials.
Those 12 lanes PCIe 2 are not enough for 6 TB3 ports, 12 lanes PCIe 3 are required to have full bandwidth.
[doublepost=1455652265][/doublepost]Apple might go with 1 TB3 controller and 2 TB2 controllers on the CPU, or 2 TB3 controllers.
And have the SSD on the PCH, although still on PCIe 2. Would be plenty fast still.
[doublepost=1455652265][/doublepost]Apple might go with 1 TB3 controller and 2 TB2 controllers on the CPU, or 2 TB3 controllers.
And have the SSD on the PCH, although still on PCIe 2. Would be plenty fast still.
Those 10 USB ports could well be the 6 USB3 provided by the chipset and 4 TB3 ports (2 controllers on the CPU).
But that was never confirmed to be the nMP, was it?
Still, it would be awesome like this, to me at least that is.
I'd prefer the SSD on the CPU of course, but you can't have it all, can you?! ;-)
Ideally, 48 lanes on the CPU would be gold, 32 for the GPUs, 12 for 3 TB3 controllers and 4 for the SSD.
A couple of the TB3 ports could even be 10GbE.
It now all depends on Apple's choice of what's important.
[doublepost=1455653597][/doublepost]This will start again the Skylake argument, with the 48 PCIe 3 lanes, but do remember that it will be only available with the Purley platform for 2S systems. But that was discussed before.
But that was never confirmed to be the nMP, was it?
Still, it would be awesome like this, to me at least that is.
I'd prefer the SSD on the CPU of course, but you can't have it all, can you?! ;-)
Ideally, 48 lanes on the CPU would be gold, 32 for the GPUs, 12 for 3 TB3 controllers and 4 for the SSD.
A couple of the TB3 ports could even be 10GbE.
It now all depends on Apple's choice of what's important.
[doublepost=1455653597][/doublepost]This will start again the Skylake argument, with the 48 PCIe 3 lanes, but do remember that it will be only available with the Purley platform for 2S systems. But that was discussed before.
You're right, they weren't enough on 6,1 for TB2.. But that is all they got. If I connect a PCIE SSD and an eGPU to my 6,1, one or both will be flakey. They oversubscribed these ports in a big way.
They might be suitable for 6 @ TB1 mice if such a thing existed but not enough bandwidth for 6 ports, pretty sure it is 3 "real" ports and even then you lose something due to the switches.
The TB2 ports on my 2014 Mini are more solid, but I only use one at a time. Much easier to connect eGPU. Apple's jiggery pokery to create an impressive number left all 6 kind of weak knee'd.
both
The SuperMicro 4028GR-TR is a case in point - a dual E5-2600 v3 system with eight PCIe 3.0 x16 double-wide graphics slots. http://www.supermicro.com/products/system/4U/4028/SYS-4028GR-TR.cfm Its PCIe topology is:
Each PCIe 3.0 x16 pipe from the CPUs is sent through a PLX switch and connected to two PCIe 3.0 x16 double-wide slots. (Note that this is better than just making each slot x8 - if the GPU pairs are not simultaneously active, they'll get full x16 bandwidth. Only when both are reading simultaneously or both writing simultaneously will they see x8 speed.)
Another option would be to put GPU-A on a PCIe 3.0 x8 slot. It's quite common to use x8 connections for GPGPUs in HPC systems. If the GPU has enough RAM for the application, very little performance is lost. (Hint: If you see a system with E5-26xx vX CPUs and eight GPUs, something is playing games with PCIe lanes.)
The SuperMicro 4028GR-TR is a case in point - a dual E5-2600 v3 system with eight PCIe 3.0 x16 double-wide graphics slots. http://www.supermicro.com/products/system/4U/4028/SYS-4028GR-TR.cfm Its PCIe topology is:
Each PCIe 3.0 x16 pipe from the CPUs is sent through a PLX switch and connected to two PCIe 3.0 x16 double-wide slots. (Note that this is better than just making each slot x8 - if the GPU pairs are not simultaneously active, they'll get full x16 bandwidth. Only when both are reading simultaneously or both writing simultaneously will they see x8 speed.)
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Apple won't go for x8 cards, even if the performance drop is minimal.
I bet they'll stick with x16 for both GPUs.
To me this is OK, I wouldn't use 6 TB ports anyway, others will have different needs of course.
Most problems would be solved with an updated PCH, something in the likes of Z170 with 20 lanes of FlexIO. Still limited by DMI but the port configuration flexibility would make up for it.
I bet they'll stick with x16 for both GPUs.
To me this is OK, I wouldn't use 6 TB ports anyway, others will have different needs of course.
Most problems would be solved with an updated PCH, something in the likes of Z170 with 20 lanes of FlexIO. Still limited by DMI but the port configuration flexibility would make up for it.
at $2,500. Roughly the same price as the starting price for a full 27'' 5K iMac at the time. Not a frequent moment in recent Apple history.
I'd imagine if Apple did push Crystalwell/ eDRAM, they were beyond early access, and into the territory of helping shape Intel make chips more suitable for Apple's needs. (As about half of Intel's CPU is now, right? (can only find old example at http://www.theregister.co.uk/2013/11/06/intel_custom_chips_update/)
http://www.techpowerup.com/reviews/AMD/R9_Fury_X_PCI-Express_Scaling/18.html Simple example of PCIe bandwidth affect on performance of GPUs. As we can see the difference is mostly marginal. But this is only gaming.
https://developer.nvidia.com/vulkan-driver
[doublepost=1455655952][/doublepost]The bandwidth issue has been studied to death by now, but there might come a time when it can make a difference, not soon though.
And I don't think Apple, even knowing that, will cut lanes to the GPUs.
It wouldn't be an "elegant" solution.
[doublepost=1455655952][/doublepost]The bandwidth issue has been studied to death by now, but there might come a time when it can make a difference, not soon though.
And I don't think Apple, even knowing that, will cut lanes to the GPUs.
It wouldn't be an "elegant" solution.
http://www.tomshardware.com/news/khronos-group-vulkan-1-api,31207.html
[doublepost=1455656811][/doublepost]http://www.anandtech.com/show/10035/vulkan-10-released
[doublepost=1455656811][/doublepost]http://www.anandtech.com/show/10035/vulkan-10-released
Right now, the Mac Pro's 6 thunderbolt 2 ports require 12 lanes of PCIe 2.0, but are only supplied with 8 lanes. This would suggest that Apple is okay supplying the thunderbolt ports with 2/3rds of their full bandwidth for use all at once.
To get to 6 TB ports Apple could have 2 thunderbolt-3 and 4 thunderbolt-2 ports which would require 4 lanes of PCIe 3.0 and 8 lanes of PCIe 2.0 (~ 16 lanes of PCIe 2.0). Based on this same logic above, apple could use a PLX splitter and provide 12 lanes of PCIe 2.0 with the following:
CPU Lanes (PCIe 3.0):
x16 GPU1
x16 GPU2
x4, PCIe 3.0 NVMe
Lanes over DMI bus (PCIe 2.0):
x1, GigE LAN1
x1, GigE LAN2
x1, Wifi
Lanes to PLX splitter:
x4 3.0 from CPU
x5 2.0 from DMI
(~13 PCIe 2.0 lanes)
1 TB3 controller, 2 TB2 controllers = 6 ports, two of which are USB-C, four of which are mini DP
OR
What if apple pipes GigE LAN and wifi through the C612's extra USB 3.0 bus internally to get 3 TB 3 controllers. This would allow for:
CPU Lanes (PCIe 3.0):
x16 GPU1
x16 GPU2
x4, PCIe 3.0 NVMe
To PLX:
x4 PCIe 3.0 from the CPU
x8 PCIe 2.0 from the DMI bus
(~16 PCIe 2.0 lanes)
3 Thunderbolt 3 controllers would require 24 lanes of PCIe 2.0. The 16 available PCIe 2.0 lanes would be 2/3rds of that required, just as is currently implemented.
To get to 6 TB ports Apple could have 2 thunderbolt-3 and 4 thunderbolt-2 ports which would require 4 lanes of PCIe 3.0 and 8 lanes of PCIe 2.0 (~ 16 lanes of PCIe 2.0). Based on this same logic above, apple could use a PLX splitter and provide 12 lanes of PCIe 2.0 with the following:
CPU Lanes (PCIe 3.0):
x16 GPU1
x16 GPU2
x4, PCIe 3.0 NVMe
Lanes over DMI bus (PCIe 2.0):
x1, GigE LAN1
x1, GigE LAN2
x1, Wifi
Lanes to PLX splitter:
x4 3.0 from CPU
x5 2.0 from DMI
(~13 PCIe 2.0 lanes)
1 TB3 controller, 2 TB2 controllers = 6 ports, two of which are USB-C, four of which are mini DP
OR
What if apple pipes GigE LAN and wifi through the C612's extra USB 3.0 bus internally to get 3 TB 3 controllers. This would allow for:
CPU Lanes (PCIe 3.0):
x16 GPU1
x16 GPU2
x4, PCIe 3.0 NVMe
To PLX:
x4 PCIe 3.0 from the CPU
x8 PCIe 2.0 from the DMI bus
(~16 PCIe 2.0 lanes)
3 Thunderbolt 3 controllers would require 24 lanes of PCIe 2.0. The 16 available PCIe 2.0 lanes would be 2/3rds of that required, just as is currently implemented.
This is incorrect. The PLX switch (not a splitter, but a full cross-bar switch with buffering, speed and protocol conversion (PCIe 3.0 uses a different signaling protocol than earlier versions)) converts 8 lanes of PCIe 3.0 to 16 lanes of full bandwidth PCIe 2.0, of which 12 lanes go to the three T-Bolt 2 controllers.
The rest of your argument has faulty math - based on not understanding what PLX switches are, and what they can and cannot do.
For example giving three T-Bolt 3 controllers 24 lanes of PCIe 2.0 would be very restrictive since the controllers have only four PCIe 3.0 inputs. They'd use 12 lanes and run at T-Bolt 2 speeds.
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OSX leaks account for 4 HS usb ports and 6 other, which translates on 4 Thunderbolt 3/USB-C Ports which requires 8 PCIE 3 lines.
That leaves us with the pcie 2 ports from the PCH (8 total) since the new chipset -supposedly - C612 already integrates GbE (2x) and USB3 (6x).
So the nnMP could be configured optimally with the following:
2 GPU from 32 cpu PCIE3 lines
4 Thunderbolt 3 /USB-C from 8 cpu PCIE3 lines
2 Thunderbolt 2 from 4 pch PCIE 2 lines
1 NVMe SSD from 4 pch PCIE 2 lines (while not as fast as on PCIE 3 still enough for 2.5 GBps which is still competitive and twice faster than cure nMP but no room to grow). Also 4 legacy USB3 directly from the PCH.
2 GbE 1 GbE from PCH.
WiFi ac and Bluetooth 4 connected as usb3 devices.
Which matches current nMP configuration 6 Thunderbolt (4 G3, 2 G2), 4 USB3 wifi ac and bt 4.
While not usual on Apple to support wifi and bt from the usb 3.0 header from the PCH, actually this is very common on the industry specially on notebooks.
Edit: checking on Intel's ARK I saw the PCH C612 only offers a Single GbE port, which could means 1)Apple using either an PCIE HUB to increase the number of PCIE lines available and get 2 more for an extra GbE controller, 2)While apple could get an custom C61x with dual GbE ports also 3)simply ditch the Second GbE since Tb3 already integrates 10GbE , alse Apple could opt for 4) only TB1 on the legacy TB ports saving 2 PCIE2 lines and assign it to GbE/WiFi/BT, I'll favor to ditch the 2nd ethernet port, since TB3's 10GbE offers an much better solution in case 1Gbps is not enough, also on small workgroups could interface a couple of TB3 Mac with USB-C cables emulating a direct 10Gbps link.
That leaves us with the pcie 2 ports from the PCH (8 total) since the new chipset -supposedly - C612 already integrates GbE (2x) and USB3 (6x).
So the nnMP could be configured optimally with the following:
2 GPU from 32 cpu PCIE3 lines
4 Thunderbolt 3 /USB-C from 8 cpu PCIE3 lines
2 Thunderbolt 2 from 4 pch PCIE 2 lines
1 NVMe SSD from 4 pch PCIE 2 lines (while not as fast as on PCIE 3 still enough for 2.5 GBps which is still competitive and twice faster than cure nMP but no room to grow). Also 4 legacy USB3 directly from the PCH.
2 GbE 1 GbE from PCH.
WiFi ac and Bluetooth 4 connected as usb3 devices.
Which matches current nMP configuration 6 Thunderbolt (4 G3, 2 G2), 4 USB3 wifi ac and bt 4.
While not usual on Apple to support wifi and bt from the usb 3.0 header from the PCH, actually this is very common on the industry specially on notebooks.
Edit: checking on Intel's ARK I saw the PCH C612 only offers a Single GbE port, which could means 1)Apple using either an PCIE HUB to increase the number of PCIE lines available and get 2 more for an extra GbE controller, 2)While apple could get an custom C61x with dual GbE ports also 3)simply ditch the Second GbE since Tb3 already integrates 10GbE , alse Apple could opt for 4) only TB1 on the legacy TB ports saving 2 PCIE2 lines and assign it to GbE/WiFi/BT, I'll favor to ditch the 2nd ethernet port, since TB3's 10GbE offers an much better solution in case 1Gbps is not enough, also on small workgroups could interface a couple of TB3 Mac with USB-C cables emulating a direct 10Gbps link.
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Quick question - what does "4 G3, 2 G2" mean? Everything else made sense, but I don't understand the acronyms here.
What I meant to say, s that the nMP account for 6 Thunderbolt 2 port 6xGen2 TB , and the expected (or my proposed nnMP) Still has 6 Thunderbolt Ports but 4xGen3 TB and 2xGen2 TB.
I have to say that my proposed (or envisioned) nnMP also saves money to apple, since simplifies the design making u necessary the PEX pcie bridge to drive the thunderbolt ports as on the nMP (and eliminates its added latency).
Also is know that TB3 chipset are cheaper than TB2 chipset on a 2x or 3x factor
Also is know that TB3 chipset are cheaper than TB2 chipset on a 2x or 3x factor
LOL (I've heard that the millennials no longer say LOL, too bad.)
Apple probably spends more on the fancy packaging for the power cord on the MP6,1 than they spend on the PLX chip.
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Remember that PLX switches, after the acquisition, skyrocketed in price.
Still, the cost is peanuts in the total cost of the machine, although Apple cares for every penny.
I still think it will come down to 2 TB3 controllers for 4 ports, the 6 USB 3 ports on the PCH, 4 lanes for the SSD on the PCH as well and another 3 for 2xGbE and WiFi/BT as the current setup.
I'd love to see 10GbE also but I don't think it's the time yet for Apple to make it standard. You'd have to give up the already fewer TB3 ports for external expansion, although you can expand on 10GbE of course.
Still, the cost is peanuts in the total cost of the machine, although Apple cares for every penny.
I still think it will come down to 2 TB3 controllers for 4 ports, the 6 USB 3 ports on the PCH, 4 lanes for the SSD on the PCH as well and another 3 for 2xGbE and WiFi/BT as the current setup.
I'd love to see 10GbE also but I don't think it's the time yet for Apple to make it standard. You'd have to give up the already fewer TB3 ports for external expansion, although you can expand on 10GbE of course.
If Sony still walks with AMD, this news bit is interesting:
http://www.eurogamer.net/articles/2016-02-16-playstation-vr-due-this-autumn-says-gamestop-ceo
2016 is the year of VR, and I am sure Apple wont miss it.
http://www.eurogamer.net/articles/2016-02-16-playstation-vr-due-this-autumn-says-gamestop-ceo
2016 is the year of VR, and I am sure Apple wont miss it.
I don't think Apple will include an Pcie switch, if so nobody will notice it on the bill.
10GbE is part of Thunderbolt 3's alt mode and Falcon Ridge, just require (as usual for 10GbE) an usb-c <=> cat 6e/fiber media converter (as sfp+ is for tipical 10GbE).
Avoiding an Pcie switch lowers Thunderbolt latency to direct pcie class latency, and only requires to resign to the 2nd GbE adapter.
I note you want the pcie switch to have 6 tb3 as well pcie3 NVMe, this maybe practical but not good from performance pov, just moving the NVMe to the PCH pcie 2 buses releases it from sharing bandwidth with tb3 devices (typically a gpu) so it's more likely this NVMe will perform better on Pcie 2 further still no products faster than 2.5GBps at least with blade form factor.
Also leaks on OSX point out only 4 usb 3.1 devices on the nnMP, this gives a solid cue Apple didn't consider am pcie3 switch. (still possible an Pcie 2 switch, but unlikely).
By restricting the nnMP to 4xTB3 2xTB2 and a single GbE port allows more optimal core notwithstanding few users will miss the 2nd GbE port having the option for an cheaper 10GbE 2nd port from TB3 compensate it fairly.
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I really don't need 6 TB3 ports, 4 is more than enough for me. I would like to see it have the same 6 ports though and PCIe3 NVMe of course, but that is highly unlikely and not the best solution, performance wise.
There's another downside of the SSD being on the PCH, not only it goes by PCIe2 (which is not really that much of a problem right now, as you say), but it also has to go through DMI (again PCIe2 like performance) concurrently with other data sources.
I also don't ever use a second GbE port but will Apple go back on the specs? I doubt it. I would see a single Intel controller instead though. But that will get you only an extra lane, not much of a gain there. Moving all comm ports to USB (to free the PCH lanes), although possible, doesn't seem the way to go.
And the reference in OS X to the number of USB ports is somewhat a nonsense, unless I'm not seeing it correctly.
It mentions I believe 6 HS ports and 4 SS ports. Well, that would be 6 USB 2.0 ports (High Speed) and 4 USB 3.0/3.1 5/10Gbps ports. That doesn't match what it's being discussed here, does it? Even the PCH doesn't have that configuration by itself, unless some ports are disabled. X99 supports upto 14 USB ports, max 6 USB 3.0 and 8 USB 2.0 - disable 2 of each and there you go. The left over ports won't even be used for anything else (GbE, WiFi, BT) unless the active USB2 ports are already only used for this. But where are the TB3 ports then? Do they even show up as USB ports at all? If they are those 4 SS ports then where are the PCH USB 3 ports?
Just wondering here..
[doublepost=1455717851][/doublepost]Another thing that troubles me right now is that even 5K HDR is not supported on DP 1.3 so this will limit the TBD3 specs. Only 4K is supported, so we'll either have 5K SDR or 4K HDR, @60Hz that is.
[doublepost=1455717982][/doublepost]FP performance numbers on Pascal, 4T DP and 12T SP? Monster...
There's another downside of the SSD being on the PCH, not only it goes by PCIe2 (which is not really that much of a problem right now, as you say), but it also has to go through DMI (again PCIe2 like performance) concurrently with other data sources.
I also don't ever use a second GbE port but will Apple go back on the specs? I doubt it. I would see a single Intel controller instead though. But that will get you only an extra lane, not much of a gain there. Moving all comm ports to USB (to free the PCH lanes), although possible, doesn't seem the way to go.
And the reference in OS X to the number of USB ports is somewhat a nonsense, unless I'm not seeing it correctly.
It mentions I believe 6 HS ports and 4 SS ports. Well, that would be 6 USB 2.0 ports (High Speed) and 4 USB 3.0/3.1 5/10Gbps ports. That doesn't match what it's being discussed here, does it? Even the PCH doesn't have that configuration by itself, unless some ports are disabled. X99 supports upto 14 USB ports, max 6 USB 3.0 and 8 USB 2.0 - disable 2 of each and there you go. The left over ports won't even be used for anything else (GbE, WiFi, BT) unless the active USB2 ports are already only used for this. But where are the TB3 ports then? Do they even show up as USB ports at all? If they are those 4 SS ports then where are the PCH USB 3 ports?
Just wondering here..
[doublepost=1455717851][/doublepost]Another thing that troubles me right now is that even 5K HDR is not supported on DP 1.3 so this will limit the TBD3 specs. Only 4K is supported, so we'll either have 5K SDR or 4K HDR, @60Hz that is.
[doublepost=1455717982][/doublepost]FP performance numbers on Pascal, 4T DP and 12T SP? Monster...
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