Got a tip for us?
Let us know
Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
A16 is 4nm?
- Thread starter scottrichardson
- Start date
- Sort by reaction score
Angstronomics wrote a very interesting article about TSMC N5 a few months ago.
Somewhat hiliarious to this thread that at the middle of the article arrive at this text excerpt.
" ...
What Does This Mean for N5?
Nothing. Continue to enjoy your 20-month old iPhone 12 and brand new M2 MacBook...."
Can nitpick at TSMC logic density numbers being 'off' if select some narrow specific logic region X on an A15 , but long term what matters is if TSMC is making incremental progress over a 18-24 month cycle or not. The density is going up over that cycle than is just fine. Apple will likely leverage that incremental improvement for a better SoC in the future.
Lots more matters here more than just density.
"... Just not as dense as assumed. Samsung’s 4LPE (H200g54) at 136.5 MTr/mm² is ever so slightly less dense than N5 but arrived 16 months later at vastly lower volumes and low reported yields. Density is only 1 metric in PPA (Power, Performance, Area). Samsung closed the gap in density but performance and power remain behind, with only a small improvement over their 7nm-class node. .."
If TSMC slightly slows the pace but keeps on steadily rolling out improvements at high yields ... that is OK too. As the N5 , N3 wafers get more expensive to process better area is going to help control costs ... which is also better also ( few folks want to pay more. Even more true with inflation impacting a wider set of stuff. )
Going too far in too large of a leap and much higher combined short term complexities didn't help Intel or Samsung in the long run.
TSMC is teetering on the line also.
" ... TSMC recently put out their N3E FINFLEX™ figures, once again in their A72 Freq Vs area plot. The rough guide given for combined area scaling contribution was 50% logic 30% SRAM 20% Analog. ....Angstronomics already has most of the critical dimensions for TSMC's 3nm offerings, and we will detail them when we can properly cover the debacle that is N3 and the walk back with N3E.
...
Of course, this unique hybrid row layout means a complete rethink of standard cell designs. Engineers have to think about which transistors in a logic block to put in each alternating low and high fin count cell rows based on device performance characteristics. Design Rule Complexity gets even more complicated. Electronic Design Automation (EDA) software has to take the hybrid rows into account. ..."
This is why tons of folks clamoring about how Apple needs to make a major architecture changes with their first move to N3 doesn't make much sense to me. Same thing for huge core count increases. Even if you have a working high level architecture design, doing N3 is going to be 'hard'. Going to the Intel strategy of 'tick/tock' is even more applicable here. Doing a 'bad' N3 implementation is a substantive risk for a wide range of shops doing design. What want to take off the table is added complexities of trying to doing major changes to the basic architecture at that same time. Many shops that lean extremely heavily on EDA tools to do all most of the work are likely to skip the initial N3-family implementations. Either the EDA tools catch up later or folks pick up the "Fin-less-Flex" options to pull it back into reach of their EDA grasp.
[ Can see why Intel apparently wanted to jump in early in N3. If they could jump in and 'tame the bronco' of N3 complexity early they would have a competitive leg up on competitors for a while. "We'll just be smarter and take on more risk to get to higher reward" is the same somewhat dangerous game they have been playing the last 4-5 years with not always positive results.
Apple's tendency to have hyper attention to detail could give them better edge in wrangling N3 into a net benefit. Also focus on rolling out same basic building blocks to multiple SoCs. However, it isn't going to be an easy 'cake walk' for them either. It probably a bit early to call N3 a 'debacle' for everybody. Pretty good chance 'somebody' was goading TSMC in this direction. The initial N3 is just more likely to be less generally useful across the whole TSMC customer base. General population more folks are going to to N4, N4P , N4X and just wait out the initial stages of N3-family. ]
Last edited:
