AMD Discussion

[Ulfric]

AMD has hired former IBM Power development lead Joshua Friedrich to work on the chipmaker's CPU-GPU integration efforts for both the data center and client sides of the house.

Friedrich, who had worked on IBM's Power server processors for more than 20 years, is working under AMD CTO Mark Papermaster in the chipmaker's engineering organization and is "responsible for driving [the company's] integrated CPU and GPU technology approach," according to Prairie.

This means Friedrich is working on the technology that will support AMD's plans to create tighter integration between its EPYC processors and Radeon Instinct GPUs on the data center side as well as its work on the SmartShift technology for mobile Ryzen and Radeon chips that was announced at CES 2020.




Scott Aylor, corporate vice president and general manager of AMD's Datacenter Solutions, previously told CRN that the company plans to more tightly integrate EPYC and Radeon Instinct, both from an architectural standpoint and a release cadence standpoint, to improve system performance.


Friedrich was most recently a distinguished engineer and director of Power technology development within IBM's Server and Technology Group, where he was "responsible for the design and delivery of IBM's Power9 processors," according to a 2017 biography published on the Institute of Electrical and Electronics Engineers' research library website.

Friedrich was the "development leader for future Power processor designs," with responsibilities including design content decisions, staffing as well as technology evaluation and interacting, according to his LinkedIn profile. He started at IBM in 1999 to work on the circuit design for the Power5 CPU.

While Friedrich's work at AMD is expected to benefit the chipmaker's data center efforts, it's also expected to help the company's client side as well.

AMD SmartShift is being pitched as a technology meant to benefit laptops with Ryzen and Radeon parts, but Patrick Moorehead, president and principal analyst at Moor Insights & Strategy, said he expects the company's development on such technology could eventually benefit servers as well.

"I'd be surprised if AMD doesn't find more ways to connect its server CPUs and GPUs," he said in a message to CRN earlier this month. "They're already closely coupling with Infinity Fabric 2 but I'd expect faster interconnects and power sharing between components."

Dominic Daninger, vice president of engineering at Nor-Tech, a high-performance computing systems integrator and AMD partner based in Burnsville, Minn., said the hiring of Friedrich is good news for AMD's long-term road map since his work likely won't start appearing in products for a while.

"It's probably a smart move on AMD's part. They're really continuing to spend money to grow that road map further out," he said. "It certainly paints a picture that AMD is going to be a significant factor for the continuing years."

AMD Hires IBM Power9 Dev Lead To Work On CPU-GPU Integration | CRN

AMD confirms to CRN that it has hired former IBM POWER9 development lead Joshua Friedrich to work on the chipmaker's CPU-GPU integration efforts.

www.crn.com

 

[cube]

Also from Intel:

AMD Announces New Senior Leadership Team

SANTA CLARA, Calif., Jan. 17, 2020 — AMD today announced several promotions and a new hire to strengthen its senior leadership team to further enable the company’s continued growth. AMD announced […]

www.hpcwire.com

 

[Ulfric]

Intel is doomed.

This is what TSMC CEO said on their on n7/6/5/3nm Roadmap.

Now I'll talk about the ramp-up of N7, N7+ and the status of N6. As N7 enters its third year of ramp, we continue to see very strong demand across a wide spectrum of products for mobile, HPC, IoT and automotive applications. Our N7+ is entering its second year of ramp. N7+ is the industry's first high-volume production with EUV photolithography technology while paving the way for N6. Our N6 provides a clear migration path for next wave N7 products as its design rules are fully compatible with N7 while providing 15% to 20% higher density, which improve power consumption when compared to N7. N6 is on track for risk production in first quarter this year and volume production before the end of this year. N6 will have 1 more EUV layer than N7+ and will further extend our N7 family well into the future. We expect our 7-nanometer family to continue to grow in its third year and contribute more than 30% of our wafer revenue in 2020.

Now allow me to talk about our N5 volume production. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about a 20% speed gain compared with 7-nanometer. N5 will adopt EUV extensively and is well on track for volume production in first half this year and with good yield. We expect a very fast and smooth ramp of N5 in the second half of this year, driven by both mobile and HPC applications. We expect 5-nanometer to contribute about 10% of our wafer revenue in 2020. N5 will be the foundry industry's most advanced solution with the best PPA. We will offer continuous enhancement to further improve the performance, power and density of our 5-nanometer technology solution into the future as well. Thus, we are confident that 5-nanometer will be another large and long-lasting node for TSMC.

Finally, I'll talk about our N3 status. We are working with customers on N3's design, and the technology development progress is going well. We have many technology options in development and we carefully evaluate all the different approaches. Our decision is based on technology, maturity, performance and cost. Our N3 will offer another full node scaling benefit in terms of performance, power and density as compared with our N5 technology. We expect our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced. We will announce more details about our N3 technology at our TSMC North America Technology Symposium on April 29.

https://www.tsmc.com/uploadfile/ir/quarterly/2019/45E7p/E/TSMC%204Q19%20transcript.pdf

 

[koyoot]

【福田昭のセミコン業界最前線】 AMDがISSCCで発表したZen2プロセッサのCPUコアとチップレットの技術

　AMDは、最新世代のマイクロプロセッサ「Zen2」のCPUコア技術とチップレット技術を、半導体回路技術の国際学会「ISSCC 2020」で2020年2月17日(米国太平洋時間)に発表した。発表は2件の講演にわかれており、まずCPUコア技術(講演番号2.1)を説明し、続いてチップレット技術(講演番号2.2)を説明するという流れだった。

pc.watch.impress.co.jp

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

fuse.wikichip.org

I think this might be interesting in the context of Zen 2 .

Effectively, AMD used 6T libraries, which are... low-power node version. What this means is that AMD achieved high-performance on a low-power node. Which is quite the achievement in itself.

Zen 2 is quite possibly one of best physical designs of few last years.

 

[deconstruct60]

【福田昭のセミコン業界最前線】 AMDがISSCCで発表したZen2プロセッサのCPUコアとチップレットの技術

　AMDは、最新世代のマイクロプロセッサ「Zen2」のCPUコア技術とチップレット技術を、半導体回路技術の国際学会「ISSCC 2020」で2020年2月17日(米国太平洋時間)に発表した。発表は2件の講演にわかれており、まずCPUコア技術(講演番号2.1)を説明し、続いてチップレット技術(講演番号2.2)を説明するという流れだった。

pc.watch.impress.co.jp

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

fuse.wikichip.org

I think this might be interesting in the context of Zen 2 .

Effectively, AMD used 6T libraries, which are... low-power node version. What this means is that AMD achieved high-performance on a low-power node. Which is quite the achievement in itself.

6T == low power node is a bit of a leap in connotation. The 'T' is the number of transistors in the base memory cell design.

That has implication on space consumption as well as power. The "high performance" here comes in part on cranking up the number of cores. Higher number of cores takes more space. So it too is a factor here.

If look at the wikichip article they have limitations on routing (have to go "up" to reroute connection between some elements ) which also consumes more space which again will influence the space consumption

Zen 2 is quite possibly one of best physical designs of few last years.

Everyone on the leading TMSC process has many of the very similar problems and issues. Again much of the "getting around the problems" was introduced by limitations of the specific process limitations involved. AMD has some custom stuff here but there is little evidence in the paper that it is all 100% custom to AMD. TMSC , EDA vendors all had a hand in this also. While there are a some tweaks AMD may have gotten for their own use the primary iteration improvements in fab libraries and EDA feature sets probably are not exclusive to AMD.

 

[koyoot]

There is no leap of faith, dec.

You clearly haven't read anything there was Dec in the WC's article, and links form it. 6T libraries are for Low-Power variant of this node. The density is part of that variant.

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

fuse.wikichip.org

Here is WikiChip's article and direct comparison, between the two nodes. As you can see clearly, 6T libraries are for Low-power variant.

High-Performance variant sacrifices the density for higher clock speeds. AMD would be able to go up to 5 GHz on this node variant, but they decided to go with the Server needs, because we have to remember that Matisse is SERVER first design. Which means: density and low power.

AMD was able to squeeze 4.5 GHz on low-power node, while also not consuming stupid amounts of power. That is in itself very impressive. It is one of the best physical designs from past few yars.

 

[Ulfric]

AMD Cézanne successor of Renoir


Let's get some of these rumoured specs down:

1. 8 cores/16 threads
   • 1.7 GHz Base Clock at 10w TDP-down
   • 2.3 GHz Base Clock at standard TDP (Standard TDP Target Nor confirmed)
   • "Enhanced I/O lanes for reduced latency" - likely a reference to PCIE 4.0
2. Semi-custom Navi 24
   • 24 CU on die
   • 4 CUs disabled on sample
   • ~950MHz on TDP-down
   • 1.2 GHz on TDP-up
   • Variable Rate Shading
   • "AI Cores"
   • RT Cores are modified from "Another SemiCustom Microsoft SOC coming out this year"

He estimates 216-223 mm2 on 7nm+

"It's being tested right now in a full device. I would say it could legitimately hit in the back-to-school season."

 

[koyoot]

Lets wait for Zen 3 first, then we will talk about next gen APUs based on this architecture .

In general, Zen 3 Engineering Samples are already going from hands to hands and are tested excessively. We know already the performance increase, and the new design's impact on certain workloads, like gaming.

But its way to early to speculate on next gen APUs .

 

[Ulfric]

Lets wait for Zen 3 first, then we will talk about next gen APUs based on this architecture .

In general, Zen 3 Engineering Samples are already going from hands to hands and are tested excessively. We know already the performance increase, and the new design's impact on certain workloads, like gaming.

But its way to early to speculate on next gen APUs .

Apparently it is based on Zen 3 but on an improved 7nm+ node with lower power envelop( 10w/25w) currently missing from A series (15w) & H series (35w/45w) APUs with a release date in this summer.

So it's not a direct successor of Renoir (I made a mistake in my initial post)

 

[koyoot]

Apparently it is based on Zen 3 but on an improved 7nm+ node with lower power envelop( 10w/25w) currently missing from A series (15w) & H series (35w/45w) APUs with a release date in this summer.

So it's not a direct successor of Renoir (I made a mistake in my initial post)

No chances. Every next gen APU is starting due next year, at the earliest. This year: only Renoir, and Van Gogh.

Also, EUV will not change suddenly the power targets for those APUs, because its defined by the needs of OEM's.

 

[Ulfric]

No chances. Every next gen APU is starting due next year, at the earliest. This year: only Renoir, and Van Gogh.

Also, EUV will not change suddenly the power targets for those APUs, because its defined by the needs of OEM's.

I mean the leak mentioned that the product is based on a Semicustom Microsoft SoC coming this year (a new release of Surface pro, surface laptop may be, Surface book clearly not as it will mostly use H series if it uses an AMD APU). SO AMD might have something under their sleeves that we normies don't know.

May be it ends up in an Apple product.

 

[koyoot]

I mean the leak mentioned that the product is based on a Semicustom Microsoft SoC coming this year (a new release of Surface pro, surface laptop may be, Surface book clearly not as it will mostly use H series if it uses an AMD APU). SO AMD might have something under their sleeves that we normies don't know.

May be it ends up in an Apple product.

Im sorry but its not a leak. The only thing that is correct is the name for it.

Surface Pro uses slightly modified Raven Ridge APUs, 4C/8T designs. If anything next gen Surface Pro will use it will be Renoir based APU.

Cezanne is correct codename for next gen APUs. But other than that it is just pure speculation.

 

[deconstruct60]

There is no leap of faith, dec.

You clearly haven't read anything there was Dec in the WC's article, and links form it. 6T libraries are for Low-Power variant of this node. The density is part of that variant.

I did read the document and understood what it was talking about. It is you who seems to be taking superficial glances and walking off into hyperbole.

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

fuse.wikichip.org

Here is WikiChip's article and direct comparison, between the two nodes. As you can see clearly, 6T libraries are for Low-power variant. [/quote]

TMSC is labeling it "low-power". That doesn't' mean it is the only one it is useful for. the "low power" is as much a relatively reference to the "high power" than put into the context of overall computational ranges. If go to the "problems as well as benefits" article which one of the problems disappear by using thee 7.5G library? None? And the resolution offsets get better or worse?


The other homework assignment for you is who else is using this "High Power" 7nm node for anything like the similar transistor budget range as the AMD CPU chiplets and same customer volume and defect targets ( in the 4B transistors range) .

High-Performance variant sacrifices the density for higher clock speeds.

chuckle. Pragmatically 7nm "low power" scarifies density too. That is one of the problems AMD had to work around with actually implementing a practical product ( as opposed to an exercise in constructing something with maximal density bragging rights with. ) .

AMD would be able to go up to 5 GHz on this node variant, but they decided to go with the Server needs, because we have to remember that Matisse is SERVER first design. Which means: density and low power.

Server needs ... which was in part the increased core count bump. You don't necessarily need high clock for more performance. That is only correlated for single threaded drag racing. Moderate to above average clocks is good for mainly parallelized and/or concurrent workloads.

Can they really go to 5 GHz and 64 cores on the same die with out thermal scaling issues ? (with HP variant)

AMD was able to squeeze 4.5 GHz on low-power node, while also not consuming stupid amounts of power. That is in itself very impressive. It is one of the best physical designs from past few yars.

It isn't whether AMD had to do substantive work to get the 7nm TMSC process to fit with their design. What would put them in the best physical design class would be a large and distinguishing gap from what everyone else who was implementing on the same process had to do. If much of this is the same across implementations it is a huge stretch to confer some unique (better than almost all the rest) honor upon AMD here.

It is hard work they put in. But many of the folks putting work into the same fab node are putting in lots of work also.

 

[koyoot]

I did read the document and understood what it was talking about. It is you who seems to be taking superficial glances and walking off into hyperbole.




TMSC is labeling it "low-power". That doesn't' mean it is the only one it is useful for. the "low power" is as much a relatively reference to the "high power" than put into the context of overall computational ranges. If go to the "problems as well as benefits" article which one of the problems disappear by using thee 7.5G library? None? And the resolution offsets get better or worse?


The other homework assignment for you is who else is using this "High Power" 7nm node for anything like the similar transistor budget range as the AMD CPU chiplets and same customer volume and defect targets ( in the 4B transistors range) .






chuckle. Pragmatically 7nm "low power" scarifies density too. That is one of the problems AMD had to work around with actually implementing a practical product ( as opposed to an exercise in constructing something with maximal density bragging rights with. ) .



Server needs ... which was in part the increased core count bump. You don't necessarily need high clock for more performance. That is only correlated for single threaded drag racing. Moderate to above average clocks is good for mainly parallelized and/or concurrent workloads.

Can they really go to 5 GHz and 64 cores on the same die with out thermal scaling issues ? (with HP variant)




It isn't whether AMD had to do substantive work to get the 7nm TMSC process to fit with their design. What would put them in the best physical design class would be a large and distinguishing gap from what everyone else who was implementing on the same process had to do. If much of this is the same across implementations it is a huge stretch to confer some unique (better than almost all the rest) honor upon AMD here.

It is hard work they put in. But many of the folks putting work into the same fab node are putting in lots of work also.

So you know better than TSMC and AMD what node TSMC made and AMD actually uses?

Maybe you do not know this, but... Apple is using 6T in their low-power Chips. And who is actually using 7.5T libraries?

Only AMD. In both Navi GPUs: 10 and 14. Only Navi 10 LE(RX 5600 XT) GPU, and mobile variants appear to be on 6T respin.

No, AMD cannot go to 5 GHz on 64 cores, but that was not the point of my post. But they could go to 5 GHz with 8C/16T design, bumping clocks to over 4 GHz.

7 nm EUV, should combine both worlds: higher desinsity and lower power alongside higher clock speeds, so here is hope that AMD will finally break the magical for them barrier of: 4 GHz base clock and 5 GHz Turbo state on single chiplet.

About the last paragraph. Show me a single other design, that clocks as high, has equal amount of performance, equally low power draw.

There is nobody in the entire world who has done anything equal, not even Apple. Matisse is one of the best physical designs from previous years, and I count into this three previous Nvidia generations of GPUs: Pascal, Volta, Turing.

 

[Falhófnir]

Intel is doomed.

This is what TSMC CEO said on their on n7/6/5/3nm Roadmap.

https://www.tsmc.com/uploadfile/ir/quarterly/2019/45E7p/E/TSMC%204Q19%20transcript.pdf

Don't know I would quite say that, Tiger Lake sounds like it might finally be a solid release on the 10nm platform, but I'm wondering if it will be too little too late for them to see off AMDs (much cheaper for similar performance) 4000 series and stem growing interest in Arm based systems. Either way I think Intel's former business model of taking the cream off the market and more or less charging what they want is dead, which is fantastic news for the consumer. Intel have had to slash desktop chip prices left right and centre as AMD have surged ahead of them, and with both AMD and Arm now viable alternatives for MBA like laptops I think we might see a similar price war around Intel's U series chips, which is a much more severe blow to Intel being a much larger and more lucrative market. This feels like the CPU market has finally opened up in an irreversible way, so I am keeping my fingers crossed for some more interesting releases from all sides in coming years!

 

[giv-as-a-ciggy-kent]

This feels like the CPU market has finally opened up in an irreversible way, so I am keeping my fingers crossed for some more interesting releases from all sides in coming years!

Doubt intel has been sitting idle after 7 years of basically nothing new architecturally speaking aside from tiny incremental improvements. Unless they went down the Boeing rabbit hole, Apple's ARM designs and AMD's zen release should have triggered some alarms over there.

Newest zen parts are killer. If intel has nothing but raw clockspeed to throw at it (which means trash margins due to low yield of higher end parts and huge price pressures, and just a huge increase in tdp negating all the efficiency improvements) then it's another netburst (shitburst) situation all over again.

 

[Falhófnir]

Doubt intel has been sitting idle after 7 years of basically nothing new architecturally speaking aside from tiny incremental improvements. Unless they went down the Boeing rabbit hole, Apple's ARM designs and AMD's zen release should have triggered some alarms over there.

Newest zen parts are killer. If intel has nothing but raw clockspeed to throw at it (which means trash margins due to low yield of higher end parts and huge price pressures, and just a huge increase in tdp negating all the efficiency improvements) then it's another netburst (shitburst) situation all over again.

I'd say yes and no on that one, it sounds like they've finally worked through most of their 10nm problems with Tiger Lake and can deliver a solid offering (though maybe still in limited volumes?) OTOH, that one rumour they'd skip ahead to 7nm by this year is looking a little unfounded, so I don't see anything that's going to magically catapult them back way out ahead of the pack.

Tiger Lake looks like it will be enough to keep them as market leaders in the ~15W ultrabook market, but they aren't far enough ahead any more that what AMD do is of no consideration to them, which could suck them in to a price war. With Windows on Arm being attractive to Microsoft as at the least a chromebook killer that's probably not an immediate/ direct threat to Intel's business model, but in the medium term it could quickly develop into one if the Windows on Arm ecosystem gains significant traction.

With desktops AMD are still striding ahead, and it's very much Intel trying to keep competitive by slashing prices. I'm still not sure what's happening with H series CPUs, if it's just Comet Lake H I think they might start to struggle against AMD here as well - though for gaming, optimisation and compatibility might keep AMD somewhat locked out for a little longer yet.

 

[koyoot]

TSMC Announces Performance-Enhanced 7nm & 5nm Process Technologies

www.anandtech.com

Radeon RX 5700: Navi and the RDNA Architecture

A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

fuse.wikichip.org

And here is confirmation my previous info that Navi 10 was made on High-Performance variant of N7 process.

 

[koyoot]

https://twitter.com/i/web/status/1231952608304259073

Thinkpad's will get Thunderbolt 3. And they have AMD APUs.

 

[Jack Burton]

https://twitter.com/i/web/status/1231952608304259073

Thinkpad's will get Thunderbolt 3. And they have AMD APUs.

Ooo, TB3? I might have to look at getting one, then.

I waiting on my final parts for my 3950x build now. Could make a good laptop companion device.

 

[jrichards1408]

https://twitter.com/i/web/status/1231952608304259073

Thinkpad's will get Thunderbolt 3. And they have AMD APUs.

I thought tb3 can only be on Intel CPU as that's who created that

 

[fat jez]

I thought tb3 can only be on Intel CPU as that's who created that

Intel made it license and royalty free: https://newsroom.intel.com/editorials/envision-world-thunderbolt-3-everywhere/#gs.xh557k

 

[koyoot]

Impact of Cache Locality

Our Gen X servers process more requests per second per core than our previous fleet. The AMD 2nd Gen EPYC 7642 processor’s large L3 cache minimizes L3 cache misses, and the time-savings add up quickly.

blog.cloudflare.com

 

[grmlin]

Looks like the Ryzen 9 4900HS is a great chip. I hope the Ryzen 4 CPUs will find their way into Thinkpads or Precisions and the like

AMD Ryzen 9 4900HS is faster than every mobile Intel Core i9 laptop in the market today according to our own benchmarks

We compare the new 7 nm AMD CPU to at least 17 different Intel laptops equipped with a 14 nm mobile Core i9 CPU and AMD almost always comes out on top. Coffee Lake-H will be behind the curve in just a few short months if AMD can maintain this performance lead across multiple OEMs.

www.notebookcheck.net

 

[koyoot]

AMD has won plenty of premium notebooks, including Dell with G15, which will also come with full 45W TDP APU and RX 5600M option.