They create an interconnect like that for the dies and then piss it out on DIMMs? That doesn't sound like anything they have done on M-series at all.
Actually, my thinking is that the UltraFusion fabric is mainly used for cache coherency between the two M1 Max dies.
Connection to the memory modules are still handled by each die's LPDDR5 memory controllers, where each M1 Max have 4 of those. With 8 memory controllers, that's where they get the 800GB/s bandwidth. The UltraFusion fabric does not handle the memory modules at all.
My thinking is that for the Mac Pro, they will likely glue 4 of those M2 Max SoCs together (with the same design as M1 Max) with their next gen UltraFusion fabric and take a hit on latency, bandwidth and power efficiency. So maybe 600GB/s per M2 Max die. With four of them, they will get 2.4TB/s of memory bandwidth, assuming all memory slots are filled. They likely will try to hide latency with larger SLC.
Imagine 1.5TB or more of high thruput memory that's available for use to the CPU, GPU, NE, and the other IP cores.
Apple isn't just simply using LPDDR5 for their memory. They have pragmatically composed a "poor man's" HBM like solution out of it at lower costs and low enough power consumption to make them happy. Pretty doubtful they are going to give that up for the Mac Pro. The capacity bumps are somewhat a byproduct of going "super wide" on the memory channels. Need to be attached to more RAM dies concurrently and that also tends to make the capacity go up.
Which is why I think they will continue to use LPDDR5. It is a practical solution for them. Maybe they are planning to use LPDDR5X for the Mac Pro for all we know, for even more bandwidth.
And as long as they are primarily hooked on LPDDR5/6 solutions then ECC is probably pragmatically out. ECC and LPDDR data bus doesn't work like DIMMs. Full fledged ECC would mean a bus bandwidth hit. Apple isn't going to take that. And they would have to be a substantively different memory controller to switch off of LPDDR to DIMMs. (again unlikely when the Ultra is literally the minimal effort to use a different die. )
I remember reading somewhere that LPDDR5 support link ECC, and LPDDR5 mandates on-chip ECC.