Geekbench 6 results and discussions

[mr_roboto]

That is backwards to the operation, though. The semantics of it is

A = B <op> (C:<shift_ct>)​

so the shift happens first. In the original AArch32, there was no discrete shift operation: it simply performed a move with a shifted/rotated source. AArch64 is structured a little differently and does have discrete shift ops. But the 64-bit version ought to be able to just feed the C operand through the barrel shifter on its way to the ALU – why it takes an extra cycle is unclear (unless it is for energy efficiency reasons, to reduce excess logic at the cost of 1 cycle for a composition that is only moderately used).

Ah, I didn't look up the actual semantics and assumed something like A = (B op C) shift N.

Barrel shifters are relatively expensive (substantially bigger than an adder), so I think that yeah, this probably just wasn't compelling enough to spend the resources on it.

 

[leman]

Ah, I didn't look up the actual semantics and assumed something like A = (B op C) shift N.

Shifting an operand is very common in integer code (address computation etc.) so it’s one of the pragmatic choices ARM does. Maximize useful information per instruction.

Barrel shifters are relatively expensive (substantially bigger than an adder), so I think that yeah, this probably just wasn't compelling enough to spend the resources on it.

If I remember correctly, “free” barrel shifter has long been a signature feature of ARM CPUs. Back in the day of in-order processing the shifter operated together with the ALU. That’s was also one of the reasons why early ARM was so fast compared to the unwieldy CISC.

Of course, superscalar execution changed things. I don’t know how modern int ALUs look like but it seems Apple ALU can do either one or the other, but not both at once.

 

[enterthemerdaverse]

Looks like Tag Heuer has made an Atom-powered watch. They still make Android watches, but it is not easy to determine if they are still Intel.


What about RISC-V would make it preferable to ARM?

Current RISC-V would need to run at something like 13Ghz to match a 3.4Ghz M2 in per core performance. But to do would make them run extremely hot so it’s not happening.

People always fantasize about small time competitors fighting and replacing the big goliaths and sometimes those people are just wrong. They need to look at the numbers.

 

[Sydde]

If I remember correctly, “free” barrel shifter has long been a signature feature of ARM CPUs. Back in the day of in-order processing the shifter operated together with the ALU. That’s was also one of the reasons why early ARM was so fast compared to the unwieldy CISC.

It was used across the ISA, to help with code density. Almost every instruction that used more than one register had operand shifting, which made the 8-bit immediates a little more useful since they could be scaled up. The 8086 had a barrel shifter, but it was half the size, before 386. It made sense to make heavy use of that big chunk of logic. Of course, the 64-bit shifter will be twice as big – but you really need a pair of fast ones in your FPUs if you want to get work done.