Intel document confirms Prescott dissipates 103 W

[ddtlm]

macrumors12345:

There is no such thing as a 1.6 Ghz Itanium 2, so I am sure that a Power4+ compares very well to it since it scores 0 on all benchmarks!

Hmmm, I thought that both models existed.

...although you should note that the Itanic scores appear to reflect the publicized "179.art cheat" that Sun found, whereas the Power4+ scores appear to be playing it straight.

Not nearly such a big effect as when Sun did it though.

These are first and foremost server chips, and nobody is going to run a server with just one thread active.

I don't think its fair to try to count processor dies when comparing Itaniums to Power4's. Thats not how they are marketed, thats not how they appear to the OS, and thats not what you pay for. If you have two Itanium2's for every Power4 die then there is no thread advantage in IBM's hands.

Wow, then you had better tell IBM, Sun, Intel, and HP this, because their long term plans are all heavily focused on producing multicore chips!

IBM's multicore chip requires a lot of external baggage for for the L3. What good is going multicore if you can't fit all the cache on the chip? What are they gaining? Intel has more processor dies in a system to get the same number of cores, but they don't have external L3 everywhere. I don't see why you are especially excited about IBM's way of doing it.

I think going multicore is a good idea, but not important at this time. Intel figures that at 90nm they can put two cores and 18 MB (or something) of L3 on a die. Thats a multicore chip I'd get excited about, well if they adopted on-die memory controllers like the Opteron, anyway. (I wonder how much heat that'll throw off!)

If Intel doesn't care about costs, then why don't they just double the L3 cache from 6 MB to 12 MB?

Well they had to draw the line somewhere and 6MB on-die is a new record.

Look, in the end it is all about trade-offs. If IBM wanted to, they could replace the second core on Power4+ with more cache, and then the single threaded SPECfp2000 scores would shoot up even higher (that benchmark, as you probably know, is highly dependent on bandwidth).

You don't think that their 32 to 128 MB L3 is enough cache? Certainly adding yet more cache (presumably L2) on die wouldn't be a big deal. You should consider the reverse of your suggestion: what if Intel had put two Itanium2 cores together with a small L2 on die, and put 128 MB L3 off-die? The Itanium2 die is primarily cache; the core is apparently smaller than that of a Pentium4 at least, I forget just how big it is.

Specifically, Itanium tries to wring everything it can out of instruction level parallelism, whereas Power4 focuses on getting performance from thread level parallelism.

Not true. The Power4 is also a very aggressive instruction-level machine, as evidenced by the internal instruction packages which some have compared to Itanium's instruction bundles. Putting two cores on a die is nice and becoming more cost effective, but doesn't accomplish anything different that putting twice as many processors into the system. Trying to compare a dual-core Power4 to a single Itanium isn't fair.

Completely unrelated question: did you say at one point that you are running OS X off of a RAID Level 0 two disk array?

Do you actually get any noticeable performance improvements out it? Honestly, it is not like I am editing huge media files on a regular basis...I was just thinking of getting some extra storage, and if I have it then I was thinking I might as well stripe it. But perhaps it is more trouble than it's worth.

Yeah it seems pretty darn fast, but I don't do it for speed so much as just to make them into one disk. I had two available 36gig SCSI's from my Linux box after one of the drives had a problem which I didn't appreciate, but I didn't want to screw with distributing my stuff on two disks, so I just striped them and back up my data. I am booting off the striped RAID, BTW. They are the only disks in the system.

 

[macrumors12345]

Originally posted by ddtlm
Hmmm, I thought that both models existed.

I believe that the 130 nm Itanic comes in 1.3, 1.4, and 1.5 Ghz flavors (and varying amounts of cache). 1.5 Ghz is definitely the fastest though.

Not nearly such a big effect as when Sun did it though.

Not quite, but still pretty big. And since it is a geometric mean, having a really big outlier vs. a big outlier is not as big a difference as you would think. I think Sun probably managed to boost their overall FP score by about 15%, and HP by about 8%. Such is benchmarking...

I don't think its fair to try to count processor dies when comparing Itaniums to Power4's. Thats not how they are marketed, thats not how they appear to the OS, and thats not what you pay for.

Okay, but I thought we were discussing it from an engineering standpoint. If you want to discuss the chips from a commercial/marketing standpoint, then the discussion is already over, because I am sure that we both agree that to date Power4 has been a commercial success while Itanic has been a commercial failure. There is not even any comparison between the two of them.

If you have two Itanium2's for every Power4 die then there is no thread advantage in IBM's hands.

You mean besides the fact that IBM is making money on Power4 and Intel/HP are hemorraging it on Itanic? Once again, from a commercial standpoint there is no contest - the relevant debate is from an engineering standpoint (in which it takes two Itanic 2's to beat a single Power4+).

What good is going multicore if you can't fit all the cache on the chip? What are they gaining?

Performance, apparently. IBM certainly could have chosen to go with a larger on-chip cache and a single core, but they ascertained that going dual core would provide better performance. And apparently, their customers (and competitors) seem to agree.

Intel has more processor dies in a system to get the same number of cores, but they don't have external L3 everywhere. I don't see why you are especially excited about IBM's way of doing it.

I wouldn't say that I am "especially excited" about it - I don't particularly care that much one way or the other, except in so far as new Power chips mean new PPC 9xx chips. ;-) All I am saying is that it certainly seems to work pretty well for them.

Intel figures that at 90nm they can put two cores and 18 MB (or something) of L3 on a die. Thats a multicore chip I'd get excited about

You're a tough customer to please, huh? Well, that is planned for 2005 - I'm sure that IBM will have plenty of goodies packed into the 90 nm Power5+ as well.

You don't think that their 32 to 128 MB L3 is enough cache?

It's not at full speed. But for the record, those figures are per MCM, i.e. 8 to 32 MB per chip (4 to 16 MB per core).

You should consider the reverse of your suggestion: what if Intel had put two Itanium2 cores together with a small L2 on die, and put 128 MB L3 off-die?

My understanding is that they want to (put two cores on a chip), which is why they are rushing the dual core chip out the door in 2005 rather than simply waiting for their originally planned multicore chip ("Tanglewood?") to ship in 2006/7.

The Itanium2 die is primarily cache; the core is apparently smaller than that of a Pentium4 at least, I forget just how big it is.

Well, that is interesting. Hmmm...so why does it dissipate so much power (even in the low end 1.3 Ghz, 1.5 MB cache versions)?

Yeah it seems pretty darn fast, but I don't do it for speed so much as just to make them into one disk.....I am booting off the striped RAID, BTW. They are the only disks in the system.

Hmmm....I'll keep that in mind when I get the G5. It will probably depend on how lazy I am feeling (do I want to reformat the disks? am I going to be that religious in backing up?). Thanks!

 

[ddtlm]

macrumors12345:

If you want to discuss the chips from a commercial/marketing standpoint, then the discussion is already over, because I am sure that we both agree that to date Power4 has been a commercial success while Itanic has been a commercial failure.

No arguement there! Heh heh. I'm sure they're billions negative at this point, and increasing all the time.

Performance, apparently. IBM certainly could have chosen to go with a larger on-chip cache and a single core, but they ascertained that going dual core would provide better performance.

So you assume Intel went the other way (single core but bring L3 on die) because it offered lower performance? I don't see how sharing a die... sharing an L2... is going to be very useful for performance (I can see it helping some, but I also see huge on-die caches being helpful).

But for the record, those figures are per MCM, i.e. 8 to 32 MB per chip (4 to 16 MB per core).

True, when all chips are in use their share is reduced, but for single-thread SPEC one core does get to use all the L3 in the MCM.

Well, that is interesting. Hmmm...so why does it dissipate so much power (even in the low end 1.3 Ghz, 1.5 MB cache versions)?

Not sure. But one of the advantages of the IA-64 ISA is that it is supposed to move a lot of the complexity out of the processor and into the compiler. I've seen more precise ideas of how big a core it is thrown around on Aceshardware forums.