Reduced instruction set processors offload some processes to the application enabling the processor to complete an instruction in a single cycle. Complicated Instruction set processors handle all tasks, requiring several cycles to complete an instruction.
This is very wrong. There is no such thing as “offloading some processes to the application.” The application has no way to “process” anything other than having the processor do the processing. And many CISC operations also execute in a single cycle.
The differences between RISC and CISC are:
1) CISC uses microcode, which means there is a state machine which decodes, for *some* instructions, single instructions into multiple, sequenced, microops, which must be issued in sequence. This requires additional pipeline stages in the instruction decoder, and increases the penalty when a branch prediction is wrong or there is any other exception that causes the pipeline to have to be flushed.
2) CISC processors have fewer registers than RISC processors, which can reduce performance depending on workload. On the other hand, when an exception or process switch occurs, the CISC penalty may be less than RISC because it there is less data to write back into RAM.
3) CISC processors support more complicated instruction formats, typically with multiple instruction lengths. Often this requires a state machine or other complicated logic to determine where a particular instruction ends; again, this complicates the instruction decoder and has associated speed penalties.
4) CISC processors allow complex addressing formats, and allow arbitrary instructions, such as ALU operations, to access memory, and not just registers. This is usually accommodated by microcode, but it nonetheless creates complications in the Load/Store unit and makes it more difficult to do things like write coalescing, etc., which affect performance.
5) Both types of processors typically have multi-cycle instructions (it’s almost impossible, for example, to have a single-cycle integer multiply or divide instruction), but RISC keeps these to a minimum, which allows for simplicity in the reservation stations and scheduling units.
6) The extra hardware necessary for CISC takes up die area and power, and increases the length of the critical paths on the chip, affecting power usage and performance. This is particularly the case where things like complicated branch predictors are necessary to make up for CISC disadvantages.
7) CISC instruction streams typically take less space to be represented in memory (10-20%, though it can vary widely depending on the nature of the instruction stream), so smaller instruction caches can be used. This is less of an issue now that the data working set typically far exceeds the instruction working set.