For what it's worth, Apple Silicon doesn't seem to have anything akin to PL1/PL2. The one behavior which maps well onto Intel power/frequency control concepts is that maximum P core clock speed is permitted only while just one P core is active, and it drops off as more P cores wake up. However, unlike Intel, this is governed on a per-cluster basis rather than the whole chip, and the worst case frequency penalty with all cores active is quite small - only about 6% for M1 family chips.
Well, therefore I was just applying the terms conceptionally and not literally - where PL1 describes the power limit, which is sustainable under current conditions - which in case of Apple depend on the current thermal conditions. In case of Intel with a pre-defined PL1 it may happen, that the SoC jumps to PL1 prematurely. But for my argument, these differences did not matter anyway.
Still I do expect, that the MBA stabilize at below 10W under nominal ambient temperatures of 20 degree Celsius - like any other passively cooled device in a laptop form factor.
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