M3 Die Shot suggests display engines take up nearly the same area as P-cores

[casperes1996]

I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.

 

[quarkysg]

I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.

Think the argument is that the crossbar is within the M2 SoC itself.

 

[mr_roboto]

I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.

I assure you it's safe to draw such conclusions based only on M2 mini capabilities. I'm just going to have to draw out a block diagram, too many people aren't familiar with how this kind of thing works inside chips.

SERDES/PHY: SERializer/DESerializer. DP, USB3, and Thunderbolt (TBT) are all based on very high speed (multi-gigabit) serial links. A SERDES converts between a parallel data path at a slower clock speed and a serial data path at a much higher clock speed. For example, in PCI Express 1.0, serial line rate is 2.5 Gbps (2.5 GHz) and parallel line rate inside a chip is usually one of 156.250 MHz (16-bit datapath) or 312.500 MHz (8-bit datapath).

Together with line drivers on the serial side of the SERDES (responsible for matching the electrical signaling standards for the respective standards), equalizers, and other mixed-mode (analog+digital circuits), this block comprises the PHY or PHYsical Layer.

eDP: Embedded DisplayPort, a variant of DP designed for internal displays of notebooks and similar things. Mac Mini motherboards connect this to a DP-to-HDMI conversion chip for the HDMI port.

DCP: Display Coprocessor, a block in Apple SoCs which periodically reads display referesh data from a frame buffer somewhere in unified memory, formats it as DisplayPort packets, and sends it through a parallel link for internally transporting DP packets.

Crossbar Switch: Has several inputs and outputs, can route any input to any output. (But not two inputs to the same output.)

The dashed lines are the connections new to M2/M3 which did not exist in M1. They absolutely must exist in M2, otherwise there would be no way for DCP 1 to drive a display connected to one of the Type C PHYs. We know it can do that because you can connect two displays to the M2 Mini's two Type C ports.

 

[mr_roboto]

Forgot to add that DCP 1 is "low spec" because it doesn't seem to support resolutions as high as DCP 2.

 

[mr_roboto]

SERDES/PHY: SERializer/DESerializer. DP, USB3, and Thunderbolt (TBT) are all based on very high speed (multi-gigabit) serial links. A SERDES converts between a parallel data path at a slower clock speed and a serial data path at a much higher clock speed. For example, in PCI Express 1.0, serial line rate is 2.5 Gbps (2.5 GHz) and parallel line rate inside a chip is usually one of 156.250 MHz (16-bit datapath) or 312.500 MHz (8-bit datapath).

Oof! I forgot what the real ratios were here and being an engineer I can't let it go.

PCIe gen 1 PHYs will usually divide by 10/20 instead of 8/16, so the parallel datapath connections to a SERDES are 10-bit @ 250 MHz or 20-bit @ 125 MHz. Why 10-bit / 20-bit? Because PCIe gen 1 uses 8b10b line coding, so each byte (8 bits) of real data gets encoded to 10 bits for transmission, and decoded back to 8 bits at the other end. The layer of the PHY which does that encoding and decoding also narrows/expands the datapaths between 8/10 or 16/20 bits.

This is probably more detail than anyone wanted.

 

[casperes1996]

This is probably more detail than anyone wanted.

Nah. I love it. Thanks for your posts. I appreciate the insights