They could include a pair of Airpod Pro's with the desktop bundle then when " Super Mega Turbo " mode is initiated flash a message on screen to " Don Airpods " 😉
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M4+ Chip Generation - Speculation Megathread [MERGED]
- Thread starter GoetzPhil
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I'm all the way there with you, bud. The amount of money I've spent jumping through my own butthole to try to build quiet PCs would buy me several Mac Studios. Now I have a parts box full of massive heatsinks, Noctua fans, etc. that I will probably never have to touch again.
Food for thought:
- The Ultra is a huge chip. There's no way a phone, watch, tablet, nor vision device could ever fit that fist-sized chip.
- Die shrinks are increasingly ineffective for some SoC components
- TSMC is investing 2.9B in 'chip packaging plant' (for 2027)
- Apple is at the forefront of low power draw/low heat designs
- Apple is noticeably absent from any UCIe like standard
It's obvious Apple and TSMC will start 'stacking' silicon. Not chiplets, Not UltraFusion. The question is when. I'm sure they're experimenting with it now, but this new TSMC plant would be part of the process in 2027. That sounds like a good estimate for when Apple products are shipping with stacked SoCs.
- The Ultra is a huge chip. There's no way a phone, watch, tablet, nor vision device could ever fit that fist-sized chip.
- Die shrinks are increasingly ineffective for some SoC components
- TSMC is investing 2.9B in 'chip packaging plant' (for 2027)
- Apple is at the forefront of low power draw/low heat designs
- Apple is noticeably absent from any UCIe like standard
It's obvious Apple and TSMC will start 'stacking' silicon. Not chiplets, Not UltraFusion. The question is when. I'm sure they're experimenting with it now, but this new TSMC plant would be part of the process in 2027. That sounds like a good estimate for when Apple products are shipping with stacked SoCs.
No way a Mini or MacBook or iPad Pro are going to fit it either. Mentioning the phone is just misdirection. The plain Mn , Pro , and Max won't fit that either.
I think that is mainly CoWoS-LSI packaging. Namely ....
" ...
For advanced packaging, C.C. Wei noted that, especially TSMC's chip on wafer on substrate (CoWoS), capacity is "very tight."
"But we are increasing our capacity as quickly as possible. And we expect these tightening will be released in next year, probably towards the end of next year, C.C. Wei had said during the Q2 call. ..."
TSM plans to invest ~$2.9B for advanced chip plant in Taiwan amid rise of AI
Taiwan Semiconductor Manufacturing (TSM) plans to invest ~T$90B ($2.87B) in an advanced packaging facility in Taiwan as AI demand heats up. Read more here
These are ginormous MI300 , Intel Data center Max GPU (Ponte Vechicoo ) , Nvidia Grace like chips TSMC is chasing aftrer. All substantively larger than the Ultra.
If the big AI training chip trend keeps up, that is mainly where TSMC's packaging money is going. Apple isn't using that tech for the Ultra (so far) . That is the other issue. Whether Apple just is going to try to stay largely inside the reticle limit for the multiple die packaging efforts. TSMC will do more of that also in the future , but much of the revenue chasing they are doing now is toward much, much larger packages.
will loop back to this toward the end.... more chiplets isn't the lowest power draw.
Apple is noticeably absent from a lot of standards. CXL . No AV!. No DisplayPort 2.0 . Abandoned OpenCL. No 3rd party GPU drivers. etc. etc. etc.
UCIe is mainly to enable logic dies from different companies to be coupled together. Apple is mainly interested in doing their own CPU , GPU , NPU, and eventually modem. They only really need an 'internal only' standard to couple those dies together. Apple's zero interesting in 3rd party GPU drivers is quite indicative of how many "other people's" dies they are hyper interested in coupling to.
Errrr, the A-series has been stacking dies for decades.
CoWoS-LSI has 'stacking' silicon but not particularly in the way you are suggesting.
Do something like decouple the memory controller logic from the main computational die? 'When' is a decent about of time.
Just stacking RAM or Cache isn't going to get Apple out of the constrained ditch they are in in trying to compete with the big dies spreading out over CoWoS variations that TSMC is spending billions to enable.
If you stack logic element dies then it is 'chiplets' that you are doing. So "Not chiplets" isn't it. UltraFusion is a relatively very low power hit for perf/watt but it is still a hit. As long as Apple is fanatically chasing maximum perf/watt , how deeply they go into the chiplet question is likely going to have problems. You have to 'give' on that front a bit ( not abandon, but just not quite so rigidly fanatical) to really seriously do a good chiplet strategy.
The Ultra is really a 'side job' that some monolithic dies are pressed into ... possibly grudgingly.
Similarly when Apple's Modem comes... not particularly likely that is going to be 'stacked on top' either. RAM is already stacked on top in most cases and if there is space in a phone for a discrete modem there is space for a bigger SoC package with both ( still could get a small decrease utilized. ) . Stacking vertically doesn't really get you more pins outs from the whole SoC. ( stack RAM which only 'talks' to the compute die doesn't have much 'outisde' pin out volume. A modems whole job is to talk to the outside/'off package' world. )
If it really is a SoC, it has a modem already. Every device you can buy is capable of 802.11 and BT, which requires demodulation from analog radio frequency signals and modulation to radio analog. Cell signal communication is not hugely different.
I think that is mainly CoWoS-LSI packaging. Namely ....
" ...
For advanced packaging, C.C. Wei noted that, especially TSMC's chip on wafer on substrate (CoWoS), capacity is "very tight."
"But we are increasing our capacity as quickly as possible. And we expect these tightening will be released in next year, probably towards the end of next year, C.C. Wei had said during the Q2 call. ..."
TSM plans to invest ~$2.9B for advanced chip plant in Taiwan amid rise of AI
Taiwan Semiconductor Manufacturing (TSM) plans to invest ~T$90B ($2.87B) in an advanced packaging facility in Taiwan as AI demand heats up. Read more hereseekingalpha.com
These are ginormous MI300 , Intel Data center Max GPU (Ponte Vechicoo ) , Nvidia Grace like chips TSMC is chasing aftrer. All substantively larger than the Ultra.
If the big AI training chip trend keeps up, that is mainly where TSMC's packaging money is going. Apple isn't using that tech for the Ultra (so far) . That is the other issue. Whether Apple just is going to try to stay largely inside the reticle limit for the multiple die packaging efforts. TSMC will do more of that also in the future , but much of the revenue chasing they are doing now is toward much, much larger packages.
Just a bit of a tangent from what I was initially replying to above. Back when Gurman said the "Extreme" was in part canned because of 'capacity' talks between Apple and TSMC ... Yeah if Apple's Extreme needed CoWoS ( and extremely likely since Ultra is barely under the 1x reticle limit with just two dies ) , then Apple would have been competing with all these , very well funded AI monster package vendors for very limited capacity. Apple couldn't have played the 'give us the big discount because we are the only volume buyer in town' card with TSMC at all. They probalby were going to have to pay top dollar for what is going to somewhat scarce for years ( unless 180 reverse in the AI market. Even recession probably won't have much impact because there are real cost savings available here. (e.g., lower labor costs) )
That four monolithic die solution didn't make a lot of sense all along and makes even less sense now. Maximum package size consumed isn't going to play well for a long while if interested in delivering at lower costs.
Apple doing a desktop 1 , 2 , 3 compute die for desktop Max , Ulra , "More than Ultra" might make sense. But if Apple is trying to keep the build costs a low as possible.. a two die cap is going to be way cheaper for them. Spreading monolithic die costs over laptops and avoiding CoWoS stampede altogether.
AI Expansion – Supply Chain Analysis For CoWoS And HBM
28 Upstream Suppliers Analyzed For Generative AI Torque AI is booming. Everyone wants more AI accelerators, and the primary limiting factor is the CoWoS advanced packaging to put the 5nm ASICs and …
www.semianalysis.com
First off, thanks for taking the time to respond. I'll defer to your expertise on the matter - but a couple of clarifying points:
I agree - the point I was making is that Apple has no definitive path for performance jumps beyond TSCM N2 (N1?). Sooner or later - say before then end of the decade, size constrained phone/watch/vision/tablet product performance increases will need a path. I'm thinking that path will be stacked silicon.
I wasn't aware of this - in what way to you mean? Memory alongside the CPU?
Isn't this what AMD is already doing?
"Decades" is a bit of an overstatement. The popular iPad 2 used an A5 SoC that was fundamentally not architected by Apple. They have only been hands-in with the chip design for a little over 10 years.
Some gaming desktops are nearing 1000w. It's just getting ridiculously inefficient.
Noise, power bill, environment, heat, and longevity of hardware are all affected by perf/watt.
1. Think of something truly exciting
2. Then think of Tim Cook
3. Then get truly underwhelmed / disappointed ... again
2. Then think of Tim Cook
3. Then get truly underwhelmed / disappointed ... again
I think it’s because we’re hitting a wall in tangible performance improvements per generation.
It’s getting harder to wring better performance out of silicon for lower power consumption every year, so what’s the easiest solution? Crank the power up and claim huge generational gains. Plus, gearing your designs to benchmark better helps, and along with dubious marketing (Apple doesn’t get leniency here either) and you’ve got the current market.
Until there’s another “breakthrough” power consumption will just continue to spiral.
Boy this aged like fine wine given current news.
It’s transformative for every aspect of electronics if it’s true. Room temperature superconductors that are made of common elements? That would mean insane efficiency just on standard processors, probably making silicon stacking unnecessary.
Also, the part I’m personally more excited about is that it could be used to make super capacitors instead of Li-Ion batteries. Extremely fast charging, better power on demand, and made of cheap materials? Hell yes.
Of course, given the impact this would have, I expect it to be a false alarm.
I agree with this entirely. There was rumors of Fabric and connecting four SoCs but it’s looking more like that was never going to happen like someone thought it would.
I believe Apple’s strategy has been and still is to ride out TSMC’s lead with them. Keep resdesigning the architecture with each process but there won’t be any innovating concepts for like a decade.
Oh! Rumors of Ray Tracing cores is interesting!
Imagining a 48GB base MacBook...
www.anandtech.com
SK Hynix Launches 24GB LPDDR5X-8500 Stacks for Smartphones, PCs, and HPC
PoP stacking (as in how phones stack DRAM on the SoC) is not interesting, not least because the wire density is low and has nasty excess capacitance.
The A16 is weird in giving up on standard PoP for something rather more sophisticated (thin glass carrier, DRAM on one side, A16 on the other, presumably TSVs linking the two). Unfortunately there are basically no good public photos opening up the A16 package :-(
If there's anything I'v learned from exploring packaging, it's that whatever you can imagine probably IS possible; Apple and TSMC make their choices based on economics not on capabilities. Right now 3D stacking is expensive, more so that other options, not least because you have to align everything very very accurately. But that will be resolved in time...
imaging the starting price of that Macbook..some people will complainImagining a 48GB base MacBook...
SK Hynix Launches 24GB LPDDR5X-8500 Stacks for Smartphones, PCs, and HPC
Imagining a 48GB base MacBook...
SK Hynix Launches 24GB LPDDR5X-8500 Stacks for Smartphones, PCs, and HPC
How many of these can the manufacturer deliver and at what price?
As far as being the 'base configuration' usage. Yeah, that would likely be a problem. But at Apple's mark-up prices for RAM there is no way that would land in a high volume conifguration.
but after there are three major vendors in the market ( Samsung , Micron , SKHynix) how much does one vendor have to supply the full load? Even if Apple doesn't buy from SKHynix if competitors don't buy 20M memory packages from Samsung and Micron that would be more left for Apple (if those were Apple's picks). Part of the issue with LPDDR5X is spreading out the demand more so than can a single vendor soak up the whole load.
SKHynix didn't start at 24GB. There is already a 16GB part This is likely just a stack with different capacity dies . SKHynix has had time to practice on just making LPDDR5X stacks in general.
AMD, Intel , MediaTek , and Qualcomm ( Snapdragon mobile and new Oryon PC ) have already been shipping SoCs that can use LPDDR5x . Apple isn't going to be the only buyer of these RAM packages. It is more the case Apple isn't going to be able to get stuff cheap ( wrangle very aggressive discounts ).
Interesting tweet and article...
If I'm not mistaken, I think Apple is best positioned to be that long-tail/edge king (I read that as mostly inference). Sure, others will have success, but if I were Apple I'd rather mine and polish this gem as opposed to spending more effort on turds like Apple News and the like.
Plus, even though Siri is pitiful in comparison to something like Chat GPT, it's not like Apple can't/won't embrace and extend that 'multi-modal LLM interaction' in Siri's (or whatever Siri turns into) futre.
If I'm not mistaken, I think Apple is best positioned to be that long-tail/edge king (I read that as mostly inference). Sure, others will have success, but if I were Apple I'd rather mine and polish this gem as opposed to spending more effort on turds like Apple News and the like.
Plus, even though Siri is pitiful in comparison to something like Chat GPT, it's not like Apple can't/won't embrace and extend that 'multi-modal LLM interaction' in Siri's (or whatever Siri turns into) futre.
Addition of room temperature quantum computing cores (QCC)?
The question is how many GQb (GigaQubits) is the baseline vs pro vs max vs ultra?
The question is how many GQb (GigaQubits) is the baseline vs pro vs max vs ultra?
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We got M2 Max and M3 Max in the same year which is insane to me. I'm "afraid" that M4 Max will hit at WWDC 2023 latest.
Jokes aside, Apple has incentive to get off this chip ASAP. I'm predicting we'll see M4 by next fall.