M4 series core count speculation

[tenthousandthings]

I've see the below posted on Reddit and wanted to know your thoughts on it?

Edit - I have seen you discussing what I think it something similar above. (Apologies I am not technical and trying to understand it all to make a purchasing decision on whether to wait for the M4. Would be grateful if someone could explain it to me like a dummy)

The M3 is built using TSCM N3B process which has a very low production yield. Only 55% of the chips are good, 45% of production is a failure. This was the only option because the N3E process will not go into production before the end of the year.

Will Apple move to N3E as soon as it becomes available? If so, they could do that during 2024. It would be logical to name the silicon on N3E as “M4” because it should use slightly less power and/or have better performance.

Well, the first thing to know is that the "55%" yield number stems from an article in April 2023 in EE Times that quoted a report from an analyst. Here is the actual quote: "At present, we believe N3 yields at TSMC for A17 and M3 processors are at around 55% [a healthy level at this stage in N3 development], and TSMC looks on schedule to boost yields by around 5+ points each quarter."

This information is from six months before the actual A17 Pro and M3+ releases. There is no subsequent information that indicates yields haven't improved as projected. The poster above who said yield problems with N3B are "well-documented" is not correct. Those numbers come from an analyst who states explicitly that yields were on track in Q1 2023.

So that 55% number is baloney. It is true that N3B is a dead end (relative to N3E/N3P, at least), but it is not because of low yields.

The other major rumor was that Apple planned to move A17 Pro/M3+ production from N3B to N3E once N3E became available. It's not impossible. It's possible Apple's designs could easily transition to N3E. I think that's extremely unlikely, but I have little basis for that assertion. Neither does anyone who says it's likely.

I think Apple will use N3P for A18. N3E won't be used at all. But that's a minority view. Regardless, this idea that they will move A17/M3 over to N3E is far-fetched, no matter what they call it. There's absolutely zero evidence for it, as far as I am aware. It's just a very old rumor that dates to the time when N3E was first announced, the typical sort of assumption that surfaces when new information is introduced.

So, in short, M4 is unlikely to be released this year on N3E, which I believe is what you are asking about. So take the plunge and buy an M3 that meets your needs. It's not inconceivable that Apple will shift to an annual cycle and M4 will launch on N3P in late 2024, but that is fantasy until Apple proves otherwise. M4 will come on N2 in 2025. It will use Nanosheet (GAA) transistors and it will address many of the concerns expressed above re: CPU versus GPU, etc.

 

[Boil]

Mac Pro Cube with A19-based M4 Extreme on N2 process for WWDC 2025, confimed...! ;^p

 

[Sydde]

N2 is expected to begin full production 2H'25, so Apple will not have any N2-based products available any earlier than April of '26. And that would be good, because 1 April '26 will be the fiftieth anniversary of Apple's founding.

Most likely, there will be M3 variants migrating to N3P (not N3E) in the next couple years, but if M4 will be on N2, it will not be making its debut any time in '25.

 

[Boil]

Apple should move to a 18 month cadence for all chips, and release all levels of product at the same time; so basically, new SoCs/models of everything every year-and-a-half...! ;^p

 

[Sydde]

Apple should move to a 18 month cadence

Gordon Moore worked for Intel. Apple has moved on from them.

 

[tenthousandthings]

N2 is expected to begin full production 2H'25, so Apple will not have any N2-based products available any earlier than April of '26. And that would be good, because 1 April '26 will be the fiftieth anniversary of Apple's founding.

Most likely, there will be M3 variants migrating to N3P (not N3E) in the next couple years, but if M4 will be on N2, it will not be making its debut any time in '25.

The recent history of TSMC’s use of production estimates in press releases supports N2 in September 2025.

TSMC projected 2H 2022 for N4P, and it was used for A16 Bionic in September 2022.

TSMC is projecting 2H 2024 for N3P, thus my insistence that A18 will be on N3P in September 2024…

So N2 could be used for A19 in September 2025, because TSMC is now saying 2H 2025 for N2. It would parallel the 2022 timeline and (if I’m right about A18 and N3P) the 2024 timeline.

No doubt, you could be right, and 2025 is unrealistic, but note that TSMC has already shifted (“pulled in”) its high-volume production estimate for N2 forward from 2026 to 2H 2025.

TSMC’s early estimates tend to be conservative, and they keep their fallback options open for as long as they can. But the shift in the estimate is a good sign for N2 sooner rather than later.

Edit to add that none of this tells us whether Apple M4 will be on N3P or N2, we’ll just have to wait and see…

 

[ChrisA]

For most Macs, I'd expect the CPU core count to remain about the same. Apple will at some point bump up the number of Neural engines from 2 to some large number.

The only reason we have hardware inside the Mac is to support the software. Where is the software going and what hardware will best support it? Mmaybe not the M4 but some later mx, what is needed is making Siri smarter and faster

Most users don't need faster CPUs, not if the Mac is only used for watching YouTube and online shopping. But a future Siri could use those neural engines and some day, maybe that is where most of the compute-power will be.

 

[Sydde]

Most users don't need faster CPUs, not if the Mac is only used for watching YouTube and online shopping.

As true as that is, there are times. My friend fills his 8Gb simply by not closing tabs (some sites a brutal, even hidden). And I remember some 20~25 years ago, my PowerMac surprised a PC person by casually running two separate audio streams at once. The capabilities of modern machines are well beyond the average person's needs, but they do notice. I liken it to having a 200W amp on your home stereo: you almost never get to 1W, but the quality is so much better at the low-power end that you are really not wasting the 199Ws you never use.

 

[johnbean393]

I wonder if the M3 Pro moving from 8+4 to 6+6 was a response to the high cost/low yield of the N3B process.

If N3E resolves these issues on the M4, then it’s possible the M4 Pro could revert back to 8+4 with clusters of 4 P-cores across the board (1 on M4, 2 on M4 Pro, 3 on M4 Max).

I don’t see Apple upping E-cores on the Max, because then you’d end up with 12 E-cores on the Ultra, which aren’t that useful on a desktop-only chip.

If there is any room to increase core counts on M4, then I suspect that will go to GPU cores as Apple is absolutely crushing it on CPU already. M4 Pro moving up to 20 makes sense (the drop from 19 to 18 again feels like a cost/yield move), I’m not sure if N3E will be enough of an efficiency/yield improvement to jump to 6-core GPU clusters? If so we could end up with 12 on the M4, 24 on the Pro and 48 on the Max.

I beg to differ.

Per die area, the e-cores pump out more performance; it actually makes sense to have a high number of e-cores for strong multi-threaded workloads while keeping a few p-cores for single-threaded workloads.

According to Geekerwan's video, the M4's p-core obtained a score of 17.56 in the SPEC 2017 floating point test, whereas the e-core got a score of 5.83. An M4 e-core takes around 0.25x the area of a p-core, but delivers 0.33x the performance.

This shows that if 1 p-core is replaced with 4 e-cores (because they take up similar die area), multi-threaded performance would be stronger by ~33%, assuming multithreading overhead is minimal.

With this conclusion, it would make sense for a chip to contain a few p-cores (4-8), then have the remaining area stuffed with e-cores. The p-cores would deliver snappy single core performance for applications like web browsing, and when workloads scale beyond them, the e-cores would deliver overall better multicore performance.

In fact, this should even deliver lower power draw. 1 p-core drew 5.63W in the SPEC 2017 floating point test, whereas 4 e-cores should draw 0.54 * 4 = 2.16W while delivering better performance.

The reasoning above suggests the M4 Max chip should perhaps forgo some of the M3 Max's current p-cores, and stuff in more e-cores to achieve higher performance at lower power.

Intel actually had a similar strategy in 12th and 13th gen, packing in more e-cores than p-cores on their high performance CPUs. This was a huge factor in 12th gen's massive generational performance leap.

For maximum performance, then, 4 of the M3 Max's p-cores could be switched out for 4 * 4 = 16 e-cores, which would result in a total of 16 + 4 = 20 e-cores, so a 8p + 20 e configuration.

Some napkin math to calculate the overall performance increase, ignoring loss in multithreading:
P-Cores: 8*1.2
New E-Cores: 4*1.33
E-Cores: 4*1.2
Total uplift: ((8*1.2+4*1.33+4*1.2)/16)-1 = 23%

This calculation assumes Apple wants to keep the CPU die area on the M4 Max roughly same as M3 Max. They could very well increase die size (much like M2 Max vs M1 Max), and put in even more p-cores / e-cores.

People often state that "on desktop chips, e-cores serve no purpose"; hopefully this explanation above adds more information to this debate.

Of course, please correct me if I'm wrong.

 

[theorist9]

This shows that if 1 p-core is replaced with 4 e-cores (because they take up similar die area), multi-threaded performance would be stronger by ~33%, assuming multithreading overhead is minimal.

The key wrinkle here is that many MT applications scale sub-linearly in performance with core count, especially as one gets to higher core counts, and thus one often can't assume minimal MT overhead. This will depend on your application, and the number of cores on which you're trying to run it.

OTOH, a benefit of MT on e-cores is that you can run all the cores at full speed (at least I'm assuming this is the case!). That's not the case for p-cores (even on AS). Thus to determine the theoretical maxiumum p-core performance for MT tasks, you need to find a MT program that does scale linearly, rather than looking at the SC p-core performance and multiplying it by the number of p-cores.

In sum, by assuming no MT overhead, you are typically underestimating the performance benefit of using p-cores over e-cores for MT tasks. And by using the SC p-core vs. SC e-core speed, you are overestimating the performance benefit of using p-cores for MT tasks (because the p-cores won't run at the SC clock speeds when all p-cores are being used).

 

[crazy dave]

I beg to differ.

Per die area, the e-cores pump out more performance; it actually makes sense to have a high number of e-cores for strong multi-threaded workloads while keeping a few p-cores for single-threaded workloads.

According to Geekerwan's video, the M4's p-core obtained a score of 17.56 in the SPEC 2017 floating point test, whereas the e-core got a score of 5.83. An M4 e-core takes around 0.25x the area of a p-core, but delivers 0.33x the performance.

This shows that if 1 p-core is replaced with 4 e-cores (because they take up similar die area), multi-threaded performance would be stronger by ~33%, assuming multithreading overhead is minimal.

With this conclusion, it would make sense for a chip to contain a few p-cores (4-8), then have the remaining area stuffed with e-cores. The p-cores would deliver snappy single core performance for applications like web browsing, and when workloads scale beyond them, the e-cores would deliver overall better multicore performance.

In fact, this should even deliver lower power draw. 1 p-core drew 5.63W in the SPEC 2017 floating point test, whereas 4 e-cores should draw 0.54 * 4 = 2.16W while delivering better performance.

The reasoning above suggests the M4 Max chip should perhaps forgo some of the M3 Max's current p-cores, and stuff in more e-cores to achieve higher performance at lower power.

Intel actually had a similar strategy in 12th and 13th gen, packing in more e-cores than p-cores on their high performance CPUs. This was a huge factor in 12th gen's massive generational performance leap.

For maximum performance, then, 4 of the M3 Max's p-cores could be switched out for 4 * 4 = 16 e-cores, which would result in a total of 16 + 4 = 20 e-cores, so a 8p + 20 e configuration.

Some napkin math to calculate the overall performance increase, ignoring loss in multithreading:
P-Cores: 8*1.2
New E-Cores: 4*1.33
E-Cores: 4*1.2
Total uplift: ((8*1.2+4*1.33+4*1.2)/16)-1 = 23%

This calculation assumes Apple wants to keep the CPU die area on the M4 Max roughly same as M3 Max. They could very well increase die size (much like M2 Max vs M1 Max), and put in even more p-cores / e-cores.

People often state that "on desktop chips, e-cores serve no purpose"; hopefully this explanation above adds more information to this debate.

Of course, please correct me if I'm wrong.

The key wrinkle here is that many MT applications scale sub-linearly in performance with core count, especially as one gets to higher core counts, and thus one often can't assume minimal MT overhead. This will depend on your application, and the number of cores on which you're trying to run it.

OTOH, a benefit of MT on e-cores is that you can run all the cores at full speed (at least I'm assuming this is the case!). That's not the case for p-cores (even on AS). Thus to determine the theoretical maxiumum p-core performance for MT tasks, you need to find a MT program that does scale linearly, rather than looking at the SC p-core performance and multiplying it by the number of p-cores.

In sum, by assuming no MT overhead, you are typically underestimating the performance benefit of using p-cores over e-cores for MT tasks. And by using the SC p-core vs. SC e-core speed, you are overestimating the performance benefit of using p-cores for MT tasks (because the p-cores won't run at the SC clock speeds when all p-cores are being used).

To back up what @theorist9 is saying here, I did an experiment using CB R24 on my cutdown M3 Max where one can alter the number of threads that gets spawned and, as a graphics-based benchmark, scales very well with thread count. Based on my own eye tests using powermetrics and the end result closely resembling the M3 Pro's using simple linear extrapolation I'm reasonably confident that when I reduced the number of threads by 4, the remaining threads all stayed on the P-cores.

When under full load for an essentially embarrassingly parallel job (it isn't quite, but close enough), the ratio of P-core to E-core MT performance is that, roughly, 4 E-cores actually delivers 1.5 P-cores worth of MT performance rather than 4 delivering 1.333. So, as @theorist9 says, for that scenario the MT performance advantage of more E-cores actually even better than what you (@johnbean393) quote*. And indeed for that kind of scalable MT workload, that's where the proliferation Intel E-cores and x86 hyper-threading in general really shines.

But to turn that around, those kinds of workloads are, increasingly, rare on the CPU, especially for desktop users. This is why GeekBench moved largely, though not completely, to task-based parallelism which would not scale as nicely with increasing core-count as they felt that wasn't reflective of how desktop users were actually using their systems, even premium ones. In those kinds of MT scenarios, a greater fraction of P-cores is still better as a smaller number of threads being run more quickly is a more efficient use of the silicon/power.

The argument that Apple's E-cores are useless on desktops stems from the idea that since desktops have much more thermal headroom and power to play with and Apple's P-cores are so efficient in comparison to x86 that Apple should just build a desktop-oriented chip with just P-cores. Personally I don't think that is right either and while I don't want to speak for @theorist9, I don't think he does either from previous conversations I've had with him but I could be wrong. So you're right that Apple's E-cores shouldn't be thought of as useless on a desktop chip. Especially since an Ultra-style or even more so an Extreme chip (if one ever gets made) would be expected to take on more of those server/workstation-like MT tasks, where Apple's E-cores could actually do quite good service. Further, even just taking care of background tasks efficiently is still nice to have on a big chip.

I'm not going to attempt to predict with any confidence what Apple will do here for its future Pro/Max/Ultra/whatever chips. Their P-cores remain industry leading Perf and Perf/watt and, in some ways, their E-cores are even more impressive. This gives Apple a good deal of flexibility in designing their clusters and I'm not knowledgeable enough to say how this will play out. I could make a case for lots of different configurations. It depends on what Apple is targeting.

*Although I'm not sure about the silicon-size differential ... I remember 4 to 1 being close for M1 P to E-core, but my impression was that the M3 E-core especially grew with the addition of another vector unit - the M3 P-core is also bigger too so I'm not sure what the relationship is anymore. Does anyone know? I didn't think they discussed that in the Geekerwan video but maybe I missed it.

 

[Boil]

So, E-cores good for MT performance, maybe Apple goes the route of more E-cores than P-cores...?

Regarding a theoretical M4 Extreme SoC, the thought now seems to be 48P/16E cores, but maybe we get the opposite, 16P/48E cores; plenty of P-cores for multi-tasking with an assortment of single-core focused programs open, and a whole bunch of E-cores to crunch away on multi-threaded tasks...?

 

[treehuggerpro]

*Although I'm not sure about the silicon-size differential ... I remember 4 to 1 being close for M1 P to E-core, but my impression was that the M3 E-core especially grew with the addition of another vector unit - the M3 P-core is also bigger too so I'm not sure what the relationship is anymore. Does anyone know? I didn't think they discussed that in the Geekerwan video but maybe I missed it.

The M3 CPU Core areas are below as a block (Cores+Cache+AMX).

(P/12 = 4.8092 mm.sq.)
(E/4 = 1.6925 mm.sq.)

Edit: @Fomalhaut - This image has been used in a few articles. Source: High Yield

 

[Fomalhaut]

The M3 CPU Core areas are below as a block (Cores+Cache+AMX).

(P/12 = 4.8092 mm.sq.)
(E/4 = 1.6925 mm.sq.)

View attachment 2395592

What is the LPDDR5 in the diagram? That sounds like RAM to me, but my understanding is that the RAM is separate to the SoC die, but right next to it on the package. Perhaps this means the memory controllers?

 

[quarkysg]

What is the LPDDR5 in the diagram?

Memory controller.

 

[crazy dave]

The M3 CPU Core areas are below as a block (Cores+Cache+AMX).

(P/12 = 4.8092 mm.sq.)
(E/4 = 1.6925 mm.sq.)

View attachment 2395592


Edit: @Fomalhaut - This image has been used in a few articles. Source: High Yield

Thanks! As a first approximation, ~3-1 works, of course any given design might change up this proportion, for instance take the number of cores to AMX: the M3 Pro has 6 P-cores per AMX (same as above) but also 6 E-cores per AMX (more), while the base M3 is 4 E-cores per AMX (same as above), but also 4 P-cores per AMX (more).

So, E-cores good for MT performance, maybe Apple goes the route of more E-cores than P-cores...?

Regarding a theoretical M4 Extreme SoC, the thought now seems to be 48P/16E cores, but maybe we get the opposite, 16P/48E cores; plenty of P-cores for multi-tasking with an assortment of single-core focused programs open, and a whole bunch of E-cores to crunch away on multi-threaded tasks...?

If you wanted to prioritize die area/power consumption ... assuming an M3 Max like proportion of 3 E-cores to 1 P-core 16P/48E would be the die area equivalent of 32 P-cores* and would perform like 34 P-cores in CB R24 (1.5/4*48 + 16). But ... 48P/16E would obviously outperform that significantly (54 P-core equivalent) at the cost of die area (~53 P-core equivalent) and power.

That's the balance.

*EDIT: with 48 E-cores and 16 P-cores they'd probably go 6 E-cores per AMX and 4 P-cores per AMX making it closer to 4-1 die area, so it'd probably be a die area equivalent of 28 P-cores, but nonetheless the main point is that you'd be trading die area for compute power - worth it depending on what else the chip is supposed to have on it (e.g. NPU/GPU/IO/etc ... size) and how many individual dies make up this hypothetical chip (monolithic vs two or more dies). For instance, @Boil rather than an Extreme config, a 16 P-core, 48 E-core would even make a great Ultra configuration: 16 P-cores for the desktop-MT workloads (more P-cores than @johnbean393 was proposing, but same concept) and 48 E-cores for the workstation/server-MT workloads would probably take up a similar die space as a 24/8 config but provide up to 25% more CB R24-like MT throughput. Sure if that's from a dual die, then 8/24 wouldn't make for a spectacular Max, but there's the rumor that Hidra will be desktop-only, so a single 8/24 die wouldn't necessarily be in a device by itself, it would only ever be paired up with a sister die. And Apple defrays the cost of not being able to repurpose the single die by itself by being its own best customer. That could work. But again, we don't know what new fangled packaging Apple may or may not deploy and Apple could have lots of different workload targets in mind. As I said previously I could justify almost any configuration, especially for the Ultra on up.

 

[Fomalhaut]

So to summarize, do we have any consensus on what the M4 Pro, Max and Ultra SKUs will be?

If the base M4 has 3P+6E and 4P+6E options, both with 10-core GPU, can we extrapolate the SKUs that Apple will release for the higher spec SoCs?

• Will the Pro and Max stay at 5/6P+6E and 10/12P+4E or increase the core count? Or increase the number of efficiency cores, as speculated in this thread?
• Do we expect an increase in binned/unbinned GPU core count, or any improvements not seen in the base M3->M4 comparison?
• Will RAM options be tied to the CPU/GPU SKU as per the M3? i.e. are we going to be in the same position of having to choose an upgraded number of CPU *and* GPU cores if we want certain RAM configurations (such as 64GB)?

 

[Confused-User]

So to summarize, do we have any consensus on what the M4 Pro, Max and Ultra SKUs will be?

If the base M4 has 3P+6E and 4P+6E options, both with 10-core GPU, can we extrapolate the SKUs that Apple will release for the higher spec SoCs?

No, you can't. You can make WAGs, but that's about it.

It's plausible that Apple will follow the pattern set by M1-M3... though even that doesn't tell you anything. Will it be more like M2 or M3? (For example: M4 Pro = 2 4-P cluster, or one 6-P cluster?)

However it's also possible that Apple will again break new ground. M4 Pro and Max might be on N3P, late in the year, and they might use even newer core designs (more likely newer GPU than newer CPU, but who knows?). It's even possible that, as @leman was predicting a while ago, they'll call them all M5 if they ship late in the year. All bets are off then.

BTW props to @theorist9 and @crazy dave for their excellent posts about SC vs. MC performance, saving me a ton of typing .

 

[crazy dave]

No, you can't. You can make WAGs, but that's about it.

It's plausible that Apple will follow the pattern set by M1-M3... though even that doesn't tell you anything. Will it be more like M2 or M3? (For example: M4 Pro = 2 4-P cluster, or one 6-P cluster?)

However it's also possible that Apple will again break new ground. M4 Pro and Max might be on N3P, late in the year, and they might use even newer core designs (more likely newer GPU than newer CPU, but who knows?). It's even possible that, as @leman was predicting a while ago, they'll call them all M5 if they ship late in the year. All bets are off then.

BTW props to @theorist9 and @crazy dave for their excellent posts about SC vs. MC performance, saving me a ton of typing .

Yup too many plausible scenarios. In fact many of the things that we know to be the case and even more so those that are rumored to be the case expand rather than contract the space of plausible scenarios. Gurman has stated that the three next dies are Donan, Brava, and Hidra. We know that Donan is the M4. It's likely that aren't seeing Macs until November. We know that N3P comes online this summer and could potentially be used for dies moving forward. We know it's cell compatible with N3E so the porting of cores from N3E to N3P should be straight forwards. However, we don't know if Apple will use N3P at all and if they do, if they will design a new set of cores for it or port the current ones. Normally we'd think of Brava and Hidra as being the Pro and Max dies respectively. However, Gurman contends that Hidra is a "desktop"-oriented design and won't come out until next summer. We know that TSMC is working heavily on new advanced packaging technologies and Apple is rumored to be a customer next year. The name Hidra certainly implies a many headed creature. Will Hidra take advantage of new packaging tech and how? How does Brava fit in? If Hidra is desktop only, is the Brava die for both Pro and Max? Will there be such a split? Is Gurman missing a die? Is he misunderstanding the relationship between the dies and Hidra will in fact be used in MacBook Pros? In which case it'll be a Max equivalent? Is Brava actually two dies, but related to each other so they share the same codename, like Brava and Brava-chop? (like M1/2 Pro was a chop of M1/2 Max but I don't remember if those dies were the given the same codename, some one else might remember) Is Brava the base die such that a single Brava makes a Pro chip and two Bravas make a Max?

Even if we were to take past history as a guide, as @Confused-User already alluded to, Apple has been tweaking and changing up its patterns and designs each generation and even within a generation: Apple experimented with higher clocks for a subset of M2 Max and M2 Ultras; Apple has constantly experimented with different Pro and Max designs (8+2 M1 Pro/Max with 2 higher frequency M1 E-cores, 8+4 M2 Pro/Max, 6+6 M3 Pro, 12+4 M3 Max); as @mr_roboto brought to my attention, Apple experimented with M3 Max E-cores (adding an extra execution unit just for the M3 Max); and of course Apple never delivered an M3 Ultra at all. Even saying that in the absence of information we should by default assume the past patterns will hold just doesn't actually tell us much detail. Apple just keeps changing the details up.

TLDR: wait for more hard info, which we may not get until close to November, if not the announcement itself depending on how leaky Apple is and what, if anything, the A18 reveals

 

[johnbean393]

Yup too many plausible scenarios. In fact many of the things that we know to be the case and even more so those that are rumored to be the case expand rather than contract the space of plausible scenarios. Gurman has stated that the three next dies are Donan, Brava, and Hidra. We know that Donan is the M4. It's likely that aren't seeing Macs until November. We know that N3P comes online this summer and could potentially be used for dies moving forward. We know it's cell compatible with N3E so the porting of cores from N3E to N3P should be straight forwards. However, we don't know if Apple will use N3P at all and if they do, if they will design a new set of cores for it or port the current ones. Normally we'd think of Brava and Hidra as being the Pro and Max dies respectively. However, Gurman contends that Hidra is a "desktop"-oriented design and won't come out until next summer. We know that TSMC is working heavily on new advanced packaging technologies and Apple is rumored to be a customer next year. The name Hidra certainly implies a many headed creature. Will Hidra take advantage of new packaging tech and how? How does Brava fit in? If Hidra is desktop only, is the Brava die for both Pro and Max? Will there be such a split? Is Gurman missing a die? Is he misunderstanding the relationship between the dies and Hidra will in fact be used in MacBook Pros? In which case it'll be a Max equivalent? Is Brava actually two dies, but related to each other so they share the same codename, like Brava and Brava-chop? (like M1/2 Pro was a chop of M1/2 Max but I don't remember if those dies were the given the same codename, some one else might remember) Is Brava the base die such that a single Brava makes a Pro chip and two Bravas make a Max?

Even if we were to take past history as a guide, as @Confused-User already alluded to, Apple has been tweaking and changing up its patterns and designs each generation and even within a generation: Apple experimented with higher clocks for a subset of M2 Max and M2 Ultras; Apple has constantly experimented with different Pro and Max designs (8+2 M1 Pro/Max with 2 higher frequency M1 E-cores, 8+4 M2 Pro/Max, 6+6 M3 Pro, 12+4 M3 Max); as @mr_roboto brought to my attention, Apple experimented with M3 Max E-cores (adding an extra execution unit just for the M3 Max); and of course Apple never delivered an M3 Ultra at all. Even saying that in the absence of information we should by default assume the past patterns will hold just doesn't actually tell us much detail. Apple just keeps changing the details up.

TLDR: wait for more hard info, which we may not get until close to November, if not the announcement itself depending on how leaky Apple is and what, if anything, the A18 reveals

I believe you are correct on that the M1/M2 generation, M1/2 Pro was the M1/2 Max die, just with half the GPU cores, media engines and memory controllers chopped off.

Back then, early leaks called what would become the M1 Max "Jade-C die", and there were rumours of a cut down version "Jade-C die chop", which turned out to be the M1 Pro. So yes, they did share a codename.

 

[Boil]

I believe you are correct on that the M1/M2 generation, M1/2 Pro was the M1/2 Max die, just with half the GPU cores, media engines and memory controllers chopped off.

Back then, early leaks called what would become the M1 Max "Jade-C die", and there were rumours of a cut down version "Jade-C die chop", which turned out to be the M1 Pro. So yes, they did share a codename.

Just to clarify, M1 Pro was never a physically chopped M1 Max die, the DESIGN was a reduced component copy of the M1 Max...

Shared codename Brava, and the supposition that two Brava dies make up the (laptop) M4 Max is exciting; the possibility of Hidra being a desktop-specific die is also quite exciting...!

Single Hidra die = (desktop) M4 Max
Dual Hidra dies = M4 Ultra
Quad Hidra dies = M4 Extreme

Now, if Apple would just slap one of those quad Hidra die M4 Extremes into a shiny new Mac Pro Cube...!