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Ah, OK. Nice catch. :)

I was going off of the slide that had been presented for X79, not board images (only saw one, and it wasn't close enough to see the PCB legend for PCIe 3.0 - LGA2011 socket was definitely visible though).

Nice to see that there are some PCIe 3.0 lanes, as Intel's chipsets have been a bit disappointing to me recently (X58/5520 on). :) The H68 definitely comes to mind... :rolleyes:


I haven't gone and dug for board images (just saw the one mentioned above).

Nice to see they did though. :) The H68/Z68 wasn't wonderful IMO, and had me concerned that they were trying to cut costs on the chipset for LGA2011 (had the impression they only addressed the storage bottleneck to a good extent <added SATA III and dealt with the DMI bandwidth issue from the previous ICH's>, and included the ICH on the same die, but stopped there).

What I don't get, is why that wasn't highligted/emphasized by Intel with the X79 leaks, as it would have generated a lot of enthusiasm for the socket. :confused:
Are we having fun yet? I am!

That sheet wasn't designed for consumers, when the final one comes it they will hype it.
 
That sheet wasn't designed for consumers, when the final one comes it they will hype it.
They still do things like that for Development Partners (i.e. board designers). :rolleyes: Been there, done that (I have gone to trade shows before and seen these sorts of presentations first hand).
 
They still do things like that for Development Partners (i.e. board designers). :rolleyes: Been there, done that (I have gone to trade shows before and seen these sorts of presentations first hand).

Now that I think of it, it would probably be on a different slide
 
Now that I think of it, it would probably be on a different slide
It looks that way (CPU slide rather than chipset).

Going to do a quick search to see if it was leaked to a public site. ;)

EDIT: OK, found a couple (not all seem to be of Intel origin, and there does seem to be a bit of confusion without the entire picture)... [search results so you guys can dig and drool to you're hearts content... :p]
  • Romley Overview (uploaded to motherboardnews - not sure by whom though)
  • it-cuiko (information on the SKU variances is interesting)

I'm getting the impression that we'll see 32 Gen 3.0 lanes used for graphics cards directly on the CPU die, while the remaining 8x Gen 3 lanes will be used for CPU to chipset communications (40 Gen 3.0 lanes total in the CPU die). The rest of the slots will be Gen 2.0 I expect, and lanes located in/provided by the X79.

Assuming this is the case, we'll get more lanes total in the system (grand total of 80 @ 40 per Gen 3.0 and Gen 2.0 spec). :D

Rather nice in the enterprise market IMO, where graphics workstation users may need more than a single GPU as well as other high speed interfaces. For example, a user that can utilize GPGPU processing (say 2 - 3 GPU's), a hardware RAID card (local storage), and FC card or 10G Ethernet card (SAN/network access), ... sort of configuration without having to compromise on what they can have as is currently the case via an Intel only solution (there are ways around it of course, such as an nVidia NF200 chip, which will add another 32 Gen 2.0 lanes to an X58 or 5520 system). :)
 
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The first part of my post was directed personally to you beause i made a citation...

I never used the word "kids"... You're attributing this to the wrong person.

The rest, and in particular that line, was directed in general to everyone who is fast to dub those who do not agree with sarcastic comments, the exact words were: "delusional kids". I was misinterpreted, maybe because english is my second language....

My definition of "pseudo-expert" on the other hand comes from the fact that sometimes there are people who form their statements on "facts" which, after a few posts, are proven to be "assumptions", in particular "incorrect assumptions".

You are surely not one of them, but you might still be proven wrong by an August release, which in my humble opinion, is still possible.
That will not mean you are not intelligent or competent. It will only be another case of "information asymmetry".

By the way it is not a race, if Apple comes out with with a new SB MacPro in August i'll buy one. If they don't, I'll buy one some months later.
 
I'd be surprised if Apple offered more than 1TB HD as standard. The $2200 27" i7 iMac has a 1TB as standard which is ridiculous in 2011 for a computer of that price. The $1200 iMac only has a 500GB HD.

I find it odd that a company that encourages users to take photos, edit home movies, and buy music and movies, can be so stingy with storage. There's not even a 3TB option on the iMacs even though you can get them on a time capsule

I've be spec'ing some Dell and HP towers for a company I work with....
i3 Sandy Bridge towers with 1-2 TB HD, 6gigs of ram, 23" LCD and wireless printers for less than $600. The company uses PC software without a Mac equivalent, and even if there was, Mac mini's can't compete in this price range.
 
Just to add that there are a couple of LGA 1155 boards that support PCIe 3.0, most likely via a discrete controller. E.g. [URL=" Fatal1ty Professional Gen 3[/URL]
MSI has a board as well. Do not ask me how you get it to work on LGA 1155 since the PCIe controller is on the processor. You are still limited to communicating over x16 + 4 PCIe 2.0 onto the processor regardless of what you do outside. This reminds me of nForce 200 and people telling me how it adds more lanes. It does not add bandwidth though.
 
...you might still be proven wrong by an August release, which in my humble opinion, is still possible.
That will not mean you are not intelligent or competent. It will only be another case of "information asymmetry".
Theoretically, I do agree it's possible. But the information currently available doesn't support this IMO (where the experience kicks in), as there's a lot of dependencies.

For example, even if Intel is working on a "custom" chip for Apple, it's far more likely to be based on an existing design. Of what's possible, Westmere or Sandy Bridge E, Sandy Bridge would make more sense in terms of increasing performance by a notable amount. Granted, Westmere variants are possible, but the only way performance would reach a notable difference from current parts, is to ramp the clock above what Intel currently offers (greater than 3.46GHz), which will produce thermal issues that have to be dealt with, and increase costs for the cooler/s used (essentially an over-clock at the factory).

By the way it is not a race, if Apple comes out with with a new SB MacPro in August i'll buy one. If they don't, I'll buy one some months later.
No it's not a race, and if Intel or Apple is trying to make it one, there's an increased potential for bugs, which doesn't do anyone any favors.

But given Intel has given Apple CPU's early in the past, Mac owners have come to expect Apple to get parts earlier than other vendors. Thus expectations have over-ruled their common sense, which could cause a higher probability of Mac users latching on to the most improbable/unreliable rumors that come along (grab onto whatever supports their desire with both hands without thinking it through or verifying the source).

I'm not very trustful of "friend of a friend" types of sources myself, as they tend not to be at all reliable. I realize this could be seen by others as jaded. But it is supported by my experiences over the years, and I've learned to trust that experience, rather than just believe in the contrary because it's what I want to happen.

Reminds of an old saying... "Wish in one hand, poop in the other, and see which one gets filled first". :eek: :D :p What does common sense and experience tell you what the outcome will most likely be? ;)

This reminds me of nForce 200 and people telling me how it adds more lanes. It does not add bandwidth though.
You're correct (more lanes/slots, but the same QPI bandwidth between the CPU and chipset). And is why I'm glad Intel seems to be addressing this (increased I/O bandwidth between the chipset and CPU).

But the slots may actually be needed (i.e. nF200 chip used), and bandwidth issues mitigated due to the fact all of the devices may not trying to communicate over the QPI bus simultaneously.

For example, think of multiple GPU's for GPGPU processing, and a RAID card (and software support of course). The RAID card may be sitting idle during the GPGPU operations, as the data was already loaded into system memory. Which means the GPU's could monopolize the QPI bandwidth without negative consequences for other I/O operations (purely bi-directional communication between system memory and GPUs via QPI).
 
You're correct (more lanes/slots, but the same QPI bandwidth between the CPU and chipset). And is why I'm glad Intel seems to be addressing this (increased I/O bandwidth between the chipset and CPU).

But the slots may actually be needed (i.e. nF200 chip used), and bandwidth issues mitigated due to the fact all of the devices may not trying to communicate over the QPI bus simultaneously.

For example, think of multiple GPU's for GPGPU processing, and a RAID card (and software support of course). The RAID card may be sitting idle during the GPGPU operations, as the data was already loaded into system memory. Which means the GPU's could monopolize the QPI bandwidth without negative consequences for other I/O operations (purely bi-directional communication between system memory and GPUs via QPI).
QPI is an entirely different game under Sandy Bridge. On Nehalem it was used to communicate to the IOH X58 chipset. The X58 handled the x36 PCIe 2.0 lanes.

On Sandy Bridge-EN, X79 is now relegated to a mere PCH. The PCI-Express controller is now onboard the processor like Lynnfield and Sandy Bridge-DT.

The LGA 1156 and LGA 1155 are very bandwidth starved once you add a discrete video solution or even dual GPUs. LGA1155/Intel 6 Series doubled the DMI bandwidth and integrated SATA 6 Gbps onboard. Panther Point (Intel 7 Series) brings USB 3.0 as well. That should be sufficient for the majority of users. (Peripheral I/O + dual x8/x8 PCI-Express 3.0 on Ivy Bridge)

X58 and X79 platforms will be for anyone that truly needs workstation levels of I/O (e.g. +6-8 hard drives, +2 GPUs, RAID). Though the entry level Sandy Bridge-EN UP processor does not appear to be that much more capable than the current Core i7 2600K. ~$300 is more than likely the starting point like the Core i7 920 back in late 2008. It is the stupid amount of PCI-Express lanes that you are looking for, platform and processor price be damned.

I have attached some rather helpful images.
 

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QPI is an entirely different game under Sandy Bridge. On Nehalem it was used to communicate to the IOH X58 chipset. The X58 handled the x36 PCIe 2.0 lanes.
Things haven't changed as much as you might think, though the changes are definitely in the right direction IMO (allows for an increase in I/O between the CPU and other components/busses in the system).

Keep in mind, that with the X58/5520, Intel managed to reduce from 4 chips in the LGA771 days (CPU, Northbridge, Southbridge, ICH) down to 3 parts (CPU, chipset, ICH).

Obviously the main factor in this was the inclusion of the memory controller to the CPU rather than residing in the Northbridge, as had been the case with FSB based architecture (QPI used to attach the CPU to the chipset, and DMI to attach the ICH to the chipset).

Now it appears they've squeezed it all down to 2 parts; CPU + chipset (aka PCH). Given this particular case (2 Intel parts to create the logic and basic feature set), the PCH isn't a simple part as it contains everything in the ICH + chipset.

Here's what I've gleaned from various bits of available information on the X79, aka PCH for Sandy Bridge E (won't cover every single detail, but it should be enough to illustrate the point):
  • PCIe controller (40 lanes of Gen 2.0 spec; 4x of them for QPI communication - see last bullet in this, as the storage option pushes this to 44 - suspect this will only be for particular SKU's). Please note, that this isn't off of the X79 slide, but a different one (linked previously in this thread - Romley Slide, that shows Gen 2.0 lanes).
  • DMI bus (communicate to subsections such as Ethernet, USB, ... controllers that have lower band requirements)
  • SATA controllers (incl. both SATA II and III)
  • SAS controller (optional - specified by a particular SKU)
  • RAID controller (optional - specified by a particular SKU)
  • 8 lane QPI for CPU communications (what I'm not sure of, is if the additional 4x PCIe lanes used for additional storage bandwidth are included in this figure or not, but I suspect it is for a 4 + 4 configuration with certain SKU's where 4x are potentially dedicated to storage I/O transfers - configurable via the system firmware)
The questionable part of all of this, is the PCIe Gen 2.0 lane count of course, as the CPU does contain Gen 3.0 lanes directly on the die. But please read on, and you'll see the logic behind the idea that this may actually be the case (I know it's long and I do apologize, but we're getting into the good stuff :D).

I know this combination seems odd (Gen 3.0 on CPU + Gen 2.0 on X79/PCH = 36 usable lanes for slots/3rd party chips of each type), but it does have merit IMO. Specifically in the case of 3rd party chips (i.e. additional SATA, SAS, Firewire, Ethernet, ...), since there is no longer a PCI bus that existed through the X58/5520 parts. Intel did this intentionally to ween designers off of it, as they did state that it was EOLed for future products in this segment.

Starting to make sense now?

Now they must use PCIe lanes to connect 3rd party chips to the system (could opt to use a PCI based part and place a PCI to PCIe bridge in place between them, but there are issues, such as PCB real estate and even cost). So I expect most designers will switch over to PCIe versions for such controllers where they haven't already done so.

Now when you consider that the PCI bus that existed previously for 3rd party chips is gone, they need some way of allowing board designers to create different market targets, and the PCIe Gen 2.0 lanes in the X79/PCH fits the need quite nicely.

And you're left with the Gen 3.0 lanes to create the slots on the board (might get lucky from time to time), and get a Gen 2.0 slot or two, depending on how many lanes remain available on the X79 and if there's PCB real estate left to place them.

What doesn't differ as much, is how QPI is used. Granted, the QPI between the X79 and CPU have no bearing on the Gen 3.0 lanes located on the CPU die, but I'd be amazed if the bandwidth is that wide directly to the CPU's controller.

That is, I suspect they're using another QPI internally between the PCIe Gen 3.0 controller and the CPU controller (based on Gen 3.0, and hopefully wider). Remember, QPI is actually designed for 20 lanes (each lane = 4 physical wires for a pair of differential signals = up to 80 wires for a full QPI; so what we got with the X58 is significantly compromised to make budget/allow for a future upgrade path without having to create an entirely new I/O interconnect at this level.

On Sandy Bridge-EN, X79 is now relegated to a mere PCH. The PCI-Express controller is now onboard the processor like Lynnfield and Sandy Bridge-DT.
They're calling the X79 a PCH, but I suspect it's more advanced than you realize (see above; uses Gen 2.0 lanes for a 3rd party chip/feature connect to replace the now eliminated PCI bus, and still uses QPI to communicate with the CPU).

I suspect the links you gave may be over-simplified in terms of how the DMI interconnect is illustrated (Block Diagram, but seems to be missing the QPI/PCIe lanes used by the X79 that are indicated in the slide that was leaked), though the jury is still out before we know for sure (confirmation by Intel would be nice).

I wish I still had as a Developer Partner. :(

The LGA 1156 and LGA 1155 are very bandwidth starved once you add a discrete video solution or even dual GPUs. LGA1155/Intel 6 Series doubled the DMI bandwidth and integrated SATA 6 Gbps onboard. Panther Point (Intel 7 Series) brings USB 3.0 as well. That should be sufficient for the majority of users. (Peripheral I/O + dual x8/x8 PCI-Express 3.0 on Ivy Bridge)

X58 and X79 platforms will be for anyone that truly needs workstation levels of I/O (e.g. +6-8 hard drives, +2 GPUs, RAID). Though the entry level Sandy Bridge-EN UP processor does not appear to be that much more capable than the current Core i7 2600K. ~$300 is more than likely the starting point like the Core i7 920 back in late 2008. It is the stupid amount of PCI-Express lanes that you are looking for, platform and processor price be damned.
I don't disagree at all.

When you look at Intel's more recent architecture designs, they're putting a lot of attention on fixing the I/O bottlenecks, not just adding cores/tinkering with clocks to increase performance. I/O bottlenecks have been the Achilles Heel of former designs, and they were aware of it. There were even issues with Nehalem, as it was an improvement, but was still a compromise (4x lanes instead of 20, which is what it was actually designed for).

Consider the above on the X79, and "stupid amount of PCIe lanes" actually makes sense (not all devoted to slots). ;) :D :p
 
Now it appears they've squeezed it all down to 2 parts; CPU + chipset (aka PCH). Given this particular case (2 Intel parts to create the logic and basic feature set), the PCH isn't a simple part as it contains everything in the ICH + chipset.
The PCH is a a lot like the older ICH. It is a super I/O chip (You might get a few more PCI-Express lanes for things like another Ethernet port, FireWire, USB 3.0 at this time.) The PCH just takes on SATA, USB, and RAID functions and not much else.


8 lane QPI for CPU communications (what I'm not sure of, is if the additional 4x PCIe lanes used for additional storage bandwidth are included in this figure or not, but I suspect it is for a 4 + 4 configuration with certain SKU's where 4x are potentially dedicated to storage I/O transfers - configurable via the system firmware)
I have seen this mentioned before as well. The number of lanes beyond the DMI 2.0 x4 ones provided still are not concrete. The standard bidirectional 20 Gbps that DMI 2.0 provides screams lacking when you are talking about up to 14 hard drives off the PCH alone.

Now they must use PCIe lanes to connect 3rd party chips to the system (could opt to use a PCI based part and place a PCI to PCIe bridge in place between them, but there are issues, such as PCB real estate and even cost). So I expect most designers will switch over to PCIe versions for such controllers where they haven't already done so.
Dropping PCI is worth noting but not terribly important. In most of the X58/P67/Z68 block diagrams I have looked over, most peripheral controllers are already on PCI-Express. The few PCI slots you do see are bridged over. There are many more boards going exclusively PCI-Express as well.

That is, I suspect they're using another QPI internally between the PCIe Gen 3.0 controller and the CPU controller (based on Gen 3.0, and hopefully wider). Remember, QPI is actually designed for 20 lanes (each lane = 4 physical wires for a pair of differential signals = up to 80 wires for a full QPI; so what we got with the X58 is significantly compromised to make budget/allow for a future upgrade path without having to create an entirely new I/O interconnect at this level.
We will have to get more information on that. Internal QPI is not something new.


I suspect the links you gave may be over-simplified in terms of how the DMI interconnect is illustrated (Block Diagram, but seems to be missing the QPI/PCIe lanes used by the X79 that are indicated in the slide that was leaked), though the jury is still out before we know for sure (confirmation by Intel would be nice).
It is sadly, solely based on what I know. I am still expecting much more than a single DMI 2.0 interface from the processor to the X79 PCH.

From what I know, X79 is also backward compatible with Nehalem/LGA 1366 processors as well.
 

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is it possible for apple to adapt 1155 Xeon E3 Sandy-Bridge in Low-end Mac Pro?
 
is it possible for apple to adapt 1155 Xeon E3 Sandy-Bridge in Low-end Mac Pro?
The benefits of the processor would be outweighed by the platform it is based on. You want a lot of PCI-Express lanes. A lot more than LGA 1156/1155 offer.

On another note, another 4 more PCIe 2.0 lanes appear on certain Sandy Bridge-DT block diagrams and appear to be unrelated to DMI 2.0. I was expecting a full 20 lanes on Sandy Bridge-DT and only saw 16 + DMI 2.0 for the consumer product.
 
LGA2011 is still the chip that we are looking towards.

It's possible that there will also be LGA 1356 chips for low-end DP market. nanofrog has already explained the complexity issue of LGA 2011 chips which adds costs so LGA 1356 would make sense. LGA 1356 would most likely have less PCIe lines and memory bandwidth though. AMD's upcoming Opteron lineup is looking pretty strong as well so maybe Intel will finally try to gain some market share in the lower-end server market.

Whether these will find their way into Mac Pro is another question though.
 
It's possible that there will also be LGA 1356 chips for low-end DP market. nanofrog has already explained the complexity issue of LGA 2011 chips which adds costs so LGA 1356 would make sense. LGA 1356 would most likely have less PCIe lines and memory bandwidth though. AMD's upcoming Opteron lineup is looking pretty strong as well so maybe Intel will finally try to gain some market share in the lower-end server market.

Whether these will find their way into Mac Pro is another question though.
I still feel that the jury is still out on LGA 1356. We still get reports that the socket exists in some sense but X79 appears to be tied to LGA 2011, with quad channel RAM no less, and possibly to the older Nehalem LGA 1366 processors as well.

I know this reflects the consumer side of things but Intel used the Core i7 9xx line-up as the dress rehearsal for the later Xeon lineup.
 
The PCH is a a lot like the older ICH. It is a super I/O chip (You might get a few more PCI-Express lanes for things like another Ethernet port, FireWire, USB 3.0 at this time.) The PCH just takes on SATA, USB, and RAID functions and not much else.
I realize how you're looking at it, and I don't entirely disagree (definitely can be viewed as a Super ICH of sorts).

But where it gets more complicated, is how many PCIe lanes it has.

If it's just a few, say 8 for example, then that's only enough for attaching 3rd party chips to add features that either aren't in Intel's parts, or the board designers chose to use another manufacturer (i.e. may go for Marvell controllers for SATA, SAS, or even hardware RAID rather than the X79 that includes the hardware RAID 5 controller). In such a case, Super ICH would apply.

Now lets consider the PCIe lanes on the CPU. Those 40 lanes of Gen 3.0 on the LGA2011 can produce say 2x 16 lane slots + 1x 8 lane slots (16/16/8) = 3 slots (5, if each group of 16x lanes is attached to 2x slots for an 16/0 or 8/8 configuration). Though fast, it's a bit limiting for that much CPU (need fast I/O to keep the cores fed), and 2x GPU cards and a RAID card would consume all the lanes. Nice and fast.

But what if that system also needs an FC, 10G Ethernet, or even an Infiniband card?

There's no slot to put it in.

In the case of Ethernet, users are stuck with whatever controller is on the board. Granted, this is more of a unique case, as it's possible enterprise boards could include a 10G Ethernet chip via PCIe lanes to the X79. But they're on the expensive side (~$70 just for a 1G chip in quantity; 10G was all "Call" - go figure :p), and won't leave any lanes if the X79 only has 8 lanes available. Example of a 10Gb/s converged controller that uses 8x lanes (Gen 3.0 compliant). So it's more likely IMO, that another card will be needed.

But if there are more lanes, say up to 40, then that's more than should be necessary for 3rd party chips. Thus allowing for additional slots @ PCIe Gen 2.0 spec. :)

Hence why I see it as having the potential of being more than just a turbo charged ICH.

Now which is correct, I'm not entirely certain yet. Need more corroboration than what I've seen so far to give this additional merit, or ideally, clear confirmation from Intel. But what is available is compelling enough to let the drooling begin. :D :p

I have seen this mentioned before as well. The number of lanes beyond the DMI 2.0 x4 ones provided still are not concrete. The standard bidirectional 20 Gbps that DMI 2.0 provides screams lacking when you are talking about up to 14 hard drives off the PCH alone.
Nothing is, as it's premature leaks (even the Intel slides leave at least as many questions as it does answers).

But in cases like this, corroboration helps to sort it all out (i.e. multiple people that have access to information covered by NDA make their own Block Diagrams that find their way on the web).

Dropping PCI is worth noting but not terribly important. In most of the X58/P67/Z68 block diagrams I have looked over, most peripheral controllers are already on PCI-Express. The few PCI slots you do see are bridged over. There are many more boards going exclusively PCI-Express as well.
I wasn't talking about slots, but rather that designers were still using the PCI bus for 3rd party chips soldered to the board (how they could do this and leave all of the slots PCIe). PCI was still usable for things like FW800, SATA (still usable for mechanical disks), 1G Ethernet, ... sorts of things.

I'm not sad to see PCI go (tired old bus that was ready to retire), but there does need to be a way for 3rd party chips to be added so board manufacturers can create a a product line for multiple price points/needs. With PCI gone, the logical successor is PCIe.

Now if the CPU is the only portion that will offer PCIe lanes (for use with 3rd party chips or slots), it won't turn out too well. Either there won't be enough slots on the board, or they won't have enough lanes available for full bandwidth for the cards located in them (i.e. trying to run an 8x lane card in a 1x or 4x slot that can actually exceed the throughput possible in a 4x lane slot).

We will have to get more information on that. Internal QPI is not something new.
No it's nothing new. Nor do we currently have that information from Intel.

But given their use of systems engineering (recycling/expanding existing tech), particularly in a subsequent new architecture (not going to re-invent every single aspect from the ground up if they can help it), internal QPI is highly probable IMO.

It is sadly, solely based on what I know. I am still expecting much more than a single DMI 2.0 interface from the processor to the X79 PCH.
I'd be amazed if this is all they did, but even Intel's own slide on the X79 that leaked clearly indicates PCIe lanes (QPI) for chip to chip communications.

This is why I'm convinced that there is at least more than DMI 2.0, which though faster, would still saturate (still has the SATA limitation, even though it's been increased to a larger value; figure its in the ~1660MB/s range for SATA, assuming the same ~340MB/s or so is reserved for the Ethernet, USB, Audio,... controllers). I hope they didn't just double everything (reduce SATA throughput limit ~1320MB/s).

The mention of PCIe lanes for SATA controller throughput would help this immensely if it's configured (seems this will only be available on the -D <Performance> and -T <RAID> variants). This may help (reposted for convenience).

From what I know, X79 is also backward compatible with Nehalem/LGA 1366 processors as well.
I would suspect so as well.

I doubt they'll discontinue the X58/5520 immediately though, as enterprise parts are typically supported for 5 years from socket debut. So it should be around about another 3 years.

There's also a financial side to this as well, as the X79 likely isn't using the same component package. Board makers won't want to use the X79 as it would mean a new board design on a design they only want to coast on (keeps it profitable vs. new design over fewer sales).

And then there's the IT side, as they want identical systems for management purposes to reduce their man hours (more people, or existing people putting in overtime).

It's possible that there will also be LGA 1356 chips for low-end DP market. nanofrog has already explained the complexity issue of LGA 2011 chips which adds costs so LGA 1356 would make sense. LGA 1356 would most likely have less PCIe lines and memory bandwidth though. AMD's upcoming Opteron lineup is looking pretty strong as well so maybe Intel will finally try to gain some market share in the lower-end server market.

Whether these will find their way into Mac Pro is another question though.
Yes, the LGA2011 is more complex. But it's also the right target to keep up with what the MP currently is, rather than taking a step backward.

The specific reason for this, is the LGA1356 parts only have 24 lanes. Fine for a mid-level server that won't need a lot of PCIe cards (primary need for slots is fast networking and/or storage; slots likely to be configured in 3 * 8x lane slots as devices like RAID, FC, and 10G Ethernet controller cards are usually 8x lane).

Not so much for a high-end workstation that users are likely to stuff to the gills, and will want at least one 16x lane slot. I can see it now... Apple announces "Brand new MP with a whopping 2 slots! Yeah!". I suspect at least a few users would want to string Steve up by the family jewels over something like that. :eek: :p

I still feel that the jury is still out on LGA 1356. We still get reports that the socket exists in some sense but X79 appears to be tied to LGA 2011, with quad channel RAM no less, and possibly to the older Nehalem LGA 1366 processors as well.
Granted, the X79 is usually mentioned with the LGA2011, but with the systems engineering that Intel seems to be employing, I actually suspect it will work with both the LGA2011 and LGA1356 parts (same interconnect implementation for the different socket CPU's).

Which translates into financial sense. One chipset that works on multiple socket CPU's, rather than a chipset per socket. Given the fact the socket count has increased, this seems the logical approach IMO to counter R&D and increased production costs (ability to better utilize existing production facilities due to fewer SKU #'s = controls production costs, such as eliminates additional tooling <converting another facility to the correct process> or need for new facility construction).

I know this reflects the consumer side of things but Intel used the Core i7 9xx line-up as the dress rehearsal for the later Xeon lineup.
Again, it's systems engineering. The consumer parts you're speaking of will almost certainly have a direct Xeon equivalent (ECC is left Enabled, otherwise no difference).

Another thing I've noticed that could be causing additional confusion with the X79, is there are 4 variants (different features, and distinguished by separate SKU's <-A, -B, -D, -T>). And the information being released, is likely focused on the Premium variant (-T SKU), which has the additional SAS/SATA controller (additional 8 ports; this portion is also in the -D variant) as well as the hardware RAID 5 controller (hardware RAID 5 = -T variant only).
 
After 3 days fighting in my head. Between "buy Sandy bridge iMac right now" and "wait for next Mac pro". It seem Mac Pro is suite me more than iMac.
 
But where it gets more complicated, is how many PCIe lanes it has...

Now lets consider the PCIe lanes on the CPU. Those 40 lanes of Gen 3.0 on the LGA2011 can produce say 2x 16 lane slots + 1x 8 lane slots (16/16/8) = 3 slots (5, if each group of 16x lanes is attached to 2x slots for an 16/0 or 8/8 configuration). Though fast, it's a bit limiting for that much CPU (need fast I/O to keep the cores fed), and 2x GPU cards and a RAID card would consume all the lanes. Nice and fast.

But what if that system also needs an FC, 10G Ethernet, or even an Infiniband card?

There's no slot to put it in.
I understand what you are trying to say. In my opinion there has to be something more than just 40 PCIe 3.0 lanes and DMI 2.0 to the X79 PCH. That or only 32 lanes are devoted to the GPU (split them however you may, x8/x8/x8/x8 for all I care) and the remaining 8 lanes are for misc. I/O. Under the PCIe 3.0 spec you are getting a maximum of ~1 GBps per lane.

In X58 you had a similar siuation where you had 32 for graphics and 4 for peripheal controllers. (36 total)

A block diagram of X79 would resolve this guessing situation we are in. I am not opposed to using the additional lanes off of the PCH for peripherals or the last 8 lanes off of the processor.

I wasn't talking about slots, but rather that designers were still using the PCI bus for 3rd party chips soldered to the board (how they could do this and leave all of the slots PCIe). PCI was still usable for things like FW800, SATA (still usable for mechanical disks), 1G Ethernet, ... sorts of things.
Slots were not my concern either. In this day and age, the only things connected to the PCI bus are the slots that are bridged over from PCI-Express. (If you have any that is.) I have yet to see peripheral controllers attached to anything but PCI-Express in the most recent boards.

I'd be amazed if this is all they did, but even Intel's own slide on the X79 that leaked clearly indicates PCIe lanes (QPI) for chip to chip communications.
Something has to be providing the additional bandwidth beyond DMI 2.0 for those extra lanes off of the X79. You are just bottlenecking over DMI 2.0 somewhat like P55 was starved to get SATA 6 Gbps and USB 3.0.

The mention of PCIe lanes for SATA controller throughput would help this immensely if it's configured (seems this will only be available on the -D <Performance> and -T <RAID> variants). This may help (reposted for convenience).
I would agree. The extra bandwidth to X79 is limited to certain SKUs. Otherwise you are just stuck with DMI 2.0.


Granted, the X79 is usually mentioned with the LGA2011, but with the systems engineering that Intel seems to be employing, I actually suspect it will work with both the LGA2011 and LGA1356 parts (same interconnect implementation for the different socket CPU's).
It seems a bit much to have two Xeon/Enthusiast sockets. LGA 2011 does appear to be suited for hardware beyond into the MP market. Then again the X79 preview we got from Computex showed LGA 2011/X79 on single socket boards. LGA 1356 leaves open the QPI channel so you are still able to go Xeon DP. It is still much to messy.

Again, it's systems engineering. The consumer parts you're speaking of will almost certainly have a direct Xeon equivalent (ECC is left Enabled, otherwise no difference).
Another note in cost savings, the Xeon sockets are not alien to the consumer market anymore either. The days of Xeon on a separate Socket 604/771 are over after Nehalem. Xeon (Nehalem) was out over 6 months after the Core i7 9xx landed. It was also a strange era where Core 2 was still around under its original price structure regardless of Core i7's existence.

In the end, I still believe anything beyond LGA 1155 is going to be overkill for most users. Even the gamers.
 
Another note in cost savings, the Xeon sockets are not alien to the consumer market anymore either. The days of Xeon on a separate Socket 604/771 are over after Nehalem. Xeon (Nehalem) was out over 6 months after the Core i7 9xx landed.
Agree!! When you looking at number of core that one processor can reach in recent years. GPGPU technology. etc. It seem dual processor isn't the only way to increase raw computing performance. especially in performance/watt aspect.
 
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In X58 you had a similar situation where you had 32 for graphics and 4 for peripheral controllers. (36 total)
Exactly my point.

Going off of the X79 slide, there's no clear indication such lanes even exist (those that are come across as X79 to CPU, not peripherals to me), yet they have to for precisely this reason.

I'm just not sure yet as to how many will be available (even the -A and -B variants will need them, as that would be more useful in a budget board; still add features to attract buyers and keep it within the per unit cost target).

A block diagram of X79 would resolve this guessing situation we are in.
Absolutely. Waiting for this could drive someone insane if they don't have access to a Developer Partner account.

I am not opposed to using the additional lanes off of the PCH for peripherals or the last 8 lanes off of the processor.
Those off of the X79 would allow for a more attractive feature set though (leaves all of the lanes off of the CPU for slot configurations).

Slots were not my concern either. In this day and age, the only things connected to the PCI bus are the slots that are bridged over from PCI-Express. (If you have any that is.) I have yet to see peripheral controllers attached to anything but PCI-Express in the most recent boards.
PCI was used more for illustrative purposes, but there could be reasons to use it (costing and technical, such as a single component consumed all of the PCIe lanes for peripheral components).

One such such example would be an LSISAS1064E (4 port, 8x lane PCIe variant). This particular situation could still arise with the X79 if there are only 4 or 8 lanes for peripherals (nothing left for anything else).

Something has to be providing the additional bandwidth beyond DMI 2.0 for those extra lanes off of the X79. You are just bottlenecking over DMI 2.0 somewhat like P55 was starved to get SATA 6 Gbps and USB 3.0.
Using nothing but DMI 2.0 would be a mistake IMO as well. Granted, it's 2x the band as DMI 1.0 in the X58/5520, but it's still a bottleneck that users will have the potential to see at this level of machine (I/O junkies).

And the mention of either a 4+4 or 8+0 (X79 to CPU communication, dedicated to storage respectively) configuration makes sense. What I don't know yet, is if this will only be the case with the -D and -T variants (hoping this isn't the case, but suspect it is).

It seems a bit much to have two Xeon/Enthusiast sockets. LGA 2011 does appear to be suited for hardware beyond into the MP market. Then again the X79 preview we got from Computex showed LGA 2011/X79 on single socket boards. LGA 1356 leaves open the QPI channel so you are still able to go Xeon DP. It is still much to messy.
Definitely need clearer information from Intel to pick out the details.

As per sockets, the market is shifting as you well know. Now we get 3 sockets (Xeon variants on all) to address these changes (entry level, mid-level, and high-end).

Another note in cost savings, the Xeon sockets are not alien to the consumer market anymore either. The days of Xeon on a separate Socket 604/771 are over after Nehalem. Xeon (Nehalem) was out over 6 months after the Core i7 9xx landed.
Absolutely. Systems engineering done right IMO (one socket + bit of nanosurgery = both consumer and enterprise variants off of the same fab without even swapping masks). :D

In the end, I still believe anything beyond LGA 1155 is going to be overkill for most users. Even the gamers.
I agree.

The enthusiasts are a small group, though a profitable one as they're willing to pay premium prices. So it makes sense (cost recovery) to allow them to buy into the LGA2011 socket, instead of just leaving it to Xeons.
 
This came to mind while driving today.

Sandy Bridge-E (Late 2011)
LGA 2011
PCIe 3.0 x32 GPU, PCIe 3.0 x8 peripherals, DMI 2.0 (40 PCIe 3.0 lanes)

LGA 1356
PCIe 3.0 x16 GPU, PCIe 3.0 x8 peripherals, DMI 2.0 (24 PCIe 3.0 lanes)

Ivy Bridge (2012)
LGA 1155
PCIe 3.0 x16 GPU, DMI 2.0 (16 PCIe 3.0 lanes)

X79 comes in various SKUs as mentioned before and the higher end ones will use the last 8 lanes for all that I/O. 40 PCI-Express 3.0 lanes will be the selling point for a single socket LGA 2011/X79 to gamers/enthusiasts. The X79-A SKU will probably fall in on those single socket LGA 2011 boards with SATA options only.

LGA 1356 will offer a lower priced Xeon DP workstation and it will not lack I/O connectivity. (If you get the right SKU.) LGA 2011 is taking everything on with all those lanes. (More I/O expansion card oriented than GPUs as mentioned before.)

I will be waiting for Ivy Bridge/Windows 8 to replace my current desktop.
 

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