For all we know at the yields they are getting the HPC crowd are getting every single chip they can make!
the Yields would have to suck really badly for this to be a problem.
300mm wafer. Assume 30 sq mm slice for an E5 just to make the numbers easier. So along diameter 10 chips. then 8 , 6 , 4 , and 2 for "half" of the wafer (less than half, but being conservative) . That boils down to 30/chips per wafer. Furthermore, assume they do
one wafer per day ( after all production is jacked up right?). That's 150 chips /week (assuming Sat/Sun off). In 3 weeks, that is 450 chips. One of these register article mention about 400 design wins. So in 3 weeks every single design win could have a production chip to test with those kinds of horrible production stats. If only 100 of those design wins are in the "check production board" status they can have about 4 chips to test with.
This is a "tock" release (**). One in which the silicon process being used is the same process that has been in place over a year. 50% yields on year old process at an Intel factory? That's the premise folks want to roll with?
These are chips that sell in the 100K-1000K per month range. Cranking out a couple hundred a month should be easy to do in spare time even with 10% yields.
The E5's probably are being blocked for marketing reasons, not yield reasons. What is more likely is that production is being ramped on the i7 variations. Those chips which could be E5s are being "flipped" into i7 extreme mode to be pushed into that inventory queue since that launch is prior to the E5 launch. I think Intel probably will separate the two to smooth out capacity demands into the respective queues and to calm the nerves of the E5 server vendors who are bit freaked about PCI-e v3.0 compliance issues wrapping up . Not because they have problems making them right now in enough numbers to test board designs.
Once the 15th November has come and gone, then we can start worrying about when the next MP will arrive!
11/15 is the Core i7 Extreme launch date; not necessarily the Xeon E5 one. Unless, Apple is going to nuke the dual package option and move to more restricted Mac Pro line up (just SP options, and chop down the parts non-ECC ram , etc. ) to boost the margin loss, then it could be a longer wait.
Past the 15th Intel could squat on the E5 launch till CES time in January. (not consumer product but bundled into that larger dog-and-pony show roll out fanfare. )
(**) In a process context. Overall it is a "tick" where the architecture changes and they hold process changes relatively constant to greatly reduce yield issues. Ivy Bridge will be more of the shrink process change where yield is going to be much more a major problem... and probably is since those target dates seem to be sliding now too.
