Agreed. That order of 3nm capacity is probably going to be used for it.M2 could be a short-lived generation. I think Apple will want to rush out M3 to try to get back to the cadence they originally wanted.
Agreed. That order of 3nm capacity is probably going to be used for it.M2 could be a short-lived generation. I think Apple will want to rush out M3 to try to get back to the cadence they originally wanted.
M2 Pro/Max rumours seem hot so if that happens I can't see M3 Pro/Max in Spring. Maybe M3 devices in Spring and M3 Pro/Max (maybe Ultra?) at WWDC. Then M4 in fall? Would put things back on track compared to the M1 launch at least.Would Apple be on schedule if it launched the M3-based 14"/16 MBP next spring and the MBA M4 next fall?
....as is my lot in life .^^ Post of the thread, currently under appreciated.
They need to have someone who knows how to type the tickets into Jira.No, as long as they have this guy it's all good.
Apple Leadership - Johny Srouji
Johny Srouji is Apple’s senior vice president of Hardware Technologies and a member of Apple’s executive leadership team. Learn more about Johny.www.apple.com
The rumor is that the M2 Pro/Max/Ultra will be built on TSMC's 3nm process. If that's true, then the M2 on the 5nm process would be a "stopgap."Hmmm. stop gap? Maybe like the Tick-Tock updates schedule that Intel did/does. One is small updates to previous design; the other is a more major change that takes longer. They work on them in parallel.
TSMC had some difficulty with 4nm and 3nm. Not to the same scale as Intel's issue with 10nm, but enough to delay shipping chips in volume. Assuming Intel stays on course, it should get back to parity with TSMC by 2025 (and could be ahead if TSMC has any delays). I wonder if Apple would consider using Intel Foundries in the future (to produce Apple Silicon - Apple isn't going back to x86).I’m fairly certain that M2 was ready to go by fall 2021. There were probably other supply constraints (display, yields etc) that prevented the new MBA to be released earlier.
Apples reliance on cutting edge is certainly its weak point, especially given the circumstances. Let’s see how things will develop.
I highly highly doubt this rumor.The rumor is that the M2 Pro/Max/Ultra will be built on TSMC's 3nm process. If that's true, then the M2 on the 5nm process would be a "stopgap."
I highly highly doubt this rumor.
N3 requires new design rules. This means Apple would have to completely redesign the A15 for N3 just for Pro, Max, Ultra. What's the goal of completely redesigning an 18-month old SoC for a new node? It takes a ton of resources to design a chip on a cutting edge. Why do it with your lowest volume chips? Why not just wait a few more months and do it with the M3?
In my opinion, it's far more likely that M2 Pro/Max/Ultra will be on N5P and M3 will be on N3.
Even so, it's interesting that the A16 will most certainly be on a variation of N5 but its corresponding M series will be on 3nm. This means Apple had to design the A16 for both the N5 and N3 processes simultaneously. There's a non-zero chance that M3 will still be on a variation of N5.
If they're 3nm and A16, then they will call it M3. The performance will be significantly different than M2. It would make no sense to call a 3nm and A16 chip as M2.Why do you assume that M2 Pro etc. will be based on A15? If the 3nm rumor is true then it’s almost guaranteed that they are based on A16.
If they're 3nm and A16, then they will call it M3. The performance will be significantly different than M2. It would make no sense to call a 3nm and A16 chip as M2.
Also, if the M2 Pro/Max comes out later this year as expected, then there's zero chance it will be 3nm.
There's nothing preventing Apple from doing anything. That doesn't mean it makes any sense.There is absolutely nothing preventing them from naming A16-derived prosumer chips “M2 Pro/Max” and then the scaled down consumer chip “M3”. These are just marketing names after all. Even has the advantage that the prosumer chips are faster and more capable and helps them get the roadmap back on track.
Either way we will see soon enough. The only thing is clear - if the upcoming prosumer chips are still A15-based, Apple will get behind the competition in terms of performance. With Zen4 and Raptor Lake on the horizon, not to mention the new GPUs, A15 cores are not cutting it anymore in the prosumer segment.
Lastly, I highly doubt that Apple could change their schedules so fast based Zen4 and Raptor Lake release info. SoCs are planned years in advance.
I personally think that if Apple can get to a place where they are releasing a new M series once every year, there's nothing AMD and Intel can do that can catch Apple. That's it. Just update once a year. Piggy back on top of the A chip.Of course, this is all conjecture and wishful thinking. I was too optimistic before hoping that M1 Pro would be more advanced than M1 and it wasn’t. I do hope for more substantial improvements in M2 prosumer chips but who knows.
I mean, even Zen4 and Raptor Lake wouldn't touch the M1 in terms of efficiency. They might beat it in raw performance but it doesn't really matter that much in a laptop, which has far higher volume than desktops.
Is it still true? The changelog of the latest version of Embree says "Using 8-wide BVH and double pumped NEON instructions on Apple M1 gives 8% performance boost"Cinebench R23 is a test that maximally favours x86 and maximally disadvantages Apple
cmaier claimed that all else equal, x86 had a 20% efficiency deficit to ARM because of all the legacy CISC instructions to support. That's consistent with what you observe with the M2 vs. 6800U. I think both are on TSMC's 5NP node.In multicore efficiency Zen3+ already gets fairly close, simply because AMD can throw more cores at the same problem and undervolt them in the process. Benchmarks show that M2 at 10W and 6800U at 12-13W get comparable scores in Cinebench R23. And sure, that's a test that maximally favours x86 and maximally disadvantages Apple, but still this suggests that the real-word efficiency difference at lower wattages is probably under 30% now. I am fairly confident that Zen4 with architectural improvements and 5nm node can reduce this to 10% (again, to be clear — I am talking about performance at low wattage). So yeah, Apple absolutely needs to continue improving their architecture to stay on top. I am curious to see how the future products will shape up. Definitely exiting things happening!
Yes it's still true. That version of embrue isn't in Cinebench yet. It will probably have to wait until a new version of Cinebench comes out. Apparently they can't alter it too much mid-version otherwise it invalidates the other scores. I'm afraid we'll have to put up with the wholly unsuitable "benchmark" being used by more clueless testers.Is it still true? The changelog of the latest version of Embree says "Using 8-wide BVH and double pumped NEON instructions on Apple M1 gives 8% performance boost"
Release Embree v3.13.4 Release · RenderKit/embree
Using 8-wide BVH and double pumped NEON instructions on Apple M1 gives 8% performance boost. Fixed binning related crash in SAH BVH builder. Added EMBREE_TBB_COMPONENT cmake option to define the co...github.com
Is it still true? The changelog of the latest version of Embree says "Using 8-wide BVH and double pumped NEON instructions on Apple M1 gives 8% performance boost"
cmaier claimed that all else equal, x86 had a 20% efficiency deficit to ARM because of all the legacy CISC instructions to support. That's consistent with what you observe with the M2 vs. 6800U. I think both are on TSMC's 5NP node.
Ah friend, we meet again. I don't know if you remember us debating on here, but we typically were arguing the same side of the same argument.Has Cinebench been updated to use the latest version of Embree? I doubt it will happen any time soon. But even if it gets updated, it’s still going to be a worst case benchmark for Apple. It still uses an AVX-to-NEON layer rather than hand optimized ARM SIMD, and it can maximally utilize the wide SIMD units of x86 CPUs as well as benefit from their faster clocks and SMT. This is the kind of workload where x86 can play all to of its advantages.
My intuition (I know, it’s not much) says that current-gen Apple Silicon would probably be 15-25% faster than now if embree were hand-optimized for ARM. But I wouldn’t be surprised if x86 CPUs (especially the high-end mobile and desktop) were still faster. As I said, massively parallel SIMD processing is not the primary strength of Apple Silicon. Nor is it the primary area of interest for most users. It’s quite funny that a benchmark that solely focuses on this one domain became the standard measure of CPU performance.
Zen3+ is N6, which is an improved N7 if I understand it correctly. I think a lot depends on which point on the efficiency curve we are comparing. The primary reason why 6800U can get closer in efficiency to M1/M2 at 10W is because it has 8 performance cores. So AMD can afford to aggressively downclock these cores more, losing out some of the per-core performance in return to a significant boost in efficiency. It we had a 8-core Zen3+ running against an 8 P-core M2 at 10 or 15 or 20W AMD would have no chance whatsoever.
But this again illustrates that performance does not exist in isolation. It all boils down to design tradeoffs. Apple has subjectively superior tech but it’s also more expensive. AMDs tech is not as good but it’s cheaper so they can afford to put more cores in an affordable package which allows them more flexibility in multicore efficiency.