it depends on what intel does. They may just move to pcie 5
They are highly likely going to move to PCIe 4 first. 1-2 years ago they had to commit to the work that will come out in 2020. PCIe 5 wasn't done then and they really didn't need more risk ( fab process had already blown up in their face).
https://www.tomshardware.com/news/i...-5.0-roadmap-leaked-granite-rapids,39403.html
You can't just 'slap' PCIe v5 on the CPU without working out a substantially faster internal bandwidth to the CPU package. ( if double the amount of data coming in you have to then move that data to the CPUs without substantially blocking. If adding more cores also then have to route all of that also without major traffic jams. ).
Sunny Cove / Ice Lake was a micro-arch change that Intel worked over last couple of years. PCIi-e v4 was relatively well know over that time so they weaved it in. PCI-e v5 is going to have to wait for the next micro-architectural bump and that isn't coming out of the pipeline until 2021.
AMD side stepped that a bit by forking off the I/O connections into a seperate chiplet and also just doubliing the width of Infinity Fabric. Trying to double the width of Ifinity Fabric again is going to be awkward. They need something else for PCI-e v5 for much of the same reasons why Intel needs something new for PCi-e v4.
Intel is moving to PCI-e v5
"... The use of PCIe Gen 5.0 is also a big element to Agilex, as it allows customers to connect directly with future PCIe 5.0 host devices, but it also allows for Intel’s new Compute eXpress Link technology, which builds upon the PCIe 5.0 physical standards. ..."
https://www.anandtech.com/show/14149/intel-agilex-10nm-fpgas-with-pcie-50-ddr5-and-cxl
But they aren't going to skip v4 on the CPU side. CXL is another relatively new wrinkle to what they have planned going forward and it will take a while to weave that into the CPUs.
If Global Foundaries hadn't thrown a curve ball at IBM's Power10 path that probably would have been the first major move to PCie v5.