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matram

macrumors 6502a
Sep 18, 2011
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That's the most likely current rumor.



The same way the memory coherency is handled within the SoC: the chips are interconnected to create one unified topology. From that perspective, the interconnected SoCs will simply work as one much larger SoC. Apple already kind of demonstrated this technology in M1 Pro and M1 Max: these are more or less scaled up m1 chips, with multiple blocks replicated.

Thank you for clarifying.

It sound to me that power consumption and heat dissipation would be such that this would only work in the Mac Pro chassis.

So any iMac or Mac Min would use the current M1Pro / Max and by this we have differentiation into three segments M1 / M1 Pro-Max / M1 2C-4C which Apple will then iterate through generations M1, M2 and so forth. Is this correct understanding?
 

altaic

Suspended
Jan 26, 2004
712
484
That strikes me as pretty odd. The die shots aren’t high resolution enough to actually reverse engineer the logic. It’s really only useful to identify known structures and IP.

So, if they’re hiding it, maybe they’re licensing IP… from AMD? Infinity Fabric? That’d surprise me, but OTOH they presumably still have a good relationship with AMD… I like it. I’ll stick it on my prediction list.
I’m curious what @leman and @cmaier has to say about IP and the silicon produced.
 
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leman

macrumors Core
Oct 14, 2008
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It sound to me that power consumption and heat dissipation would be such that this would only work in the Mac Pro chassis.

So any iMac or Mac Min would use the current M1Pro / Max and by this we have differentiation into three segments M1 / M1 Pro-Max / M1 2C-4C which Apple will then iterate through generations M1, M2 and so forth. Is this correct understanding?

Or a bigger Mac chassis. A single M1 Max is ~ 90W (with DRAM), which will still be under 200W combined. This is more than within the capacity of the 27" iMac (which currently has to cool a 125W CPU and a ~ 100+W GPU).


So, if they’re hiding it, maybe they’re licensing IP… from AMD? Infinity Fabric? That’d surprise me, but OTOH they presumably still have a good relationship with AMD… I like it. I’ll stick it on my prediction list.

Why would they license Infinity Fabric from AMD? They have their own stuff and it seems to work very well. As to chip interconnect, Apple has patents which are more advanced that the tech AMD currently uses (Apple's interconnect patents are roughly comparable to Intel's "compute tiles" coming with Meteor Lake). AMD currently connects multiple chips by rooting the signals though the interposer and via a shared interface chip. Apple and Intel are connecting the chips directly via bridges.
 
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altaic

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Jan 26, 2004
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Why would they license Infinity Fabric from AMD? They have their own stuff and it seems to work very well. As to chip interconnect, Apple has patents which are more advanced that the tech AMD currently uses (Apple's interconnect patents are roughly comparable to Intel's "compute tiles" coming with Meteor Lake). AMD currently connects multiple chips by rooting the signals though the interposer and via a shared interface chip. Apple and Intel are connecting the chips directly via bridges.
I agree, hence “it strikes me as pretty odd”. Do you have anything useful to say about the prevailing theory that the lower part of the M1 Max die pic has been doctored to hide the future interconnect? What you responded to was my best effort.
 

leman

macrumors Core
Oct 14, 2008
19,521
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I agree, hence “it strikes me as pretty odd”. Do you have anything useful to say about the prevailing theory that the lower part of the M1 Max die pic has been doctored to hide the future interconnect? What you responded to was my best effort.

I don't know anything about chip design, so I doubt I can add anything of value here. I've heard though that these are not real die shots but instead photoshopped images.
 

altaic

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Jan 26, 2004
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I don't know anything about chip design, so I doubt I can add anything of value here. I've heard though that these are not real die shots but instead photoshopped images.
I guess we’ll see pretty soon.
 

Populus

macrumors 603
Aug 24, 2012
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Do you think the M1 Pro and M1 Max use the new efficiency cores from the A15?
This is a very interesting question, and one of the reasons I’m waiting for the M2 chips on next year devices (iPad Pro and MacBook Air), as I’m pretty sure the M2 will include those A15 efficiency cores.

I don’t know if they are using them on the M1 Pro / Max, maybe that’s the reason they’re including just two of them, but honestly I would bet the architecture is the same as the M1 chip. The same cores, I mean.

We will see how the M2 turns out to be, if it’s a radical improvement based on the A16 architecture, or just a minor update like the A15 at a better litography (3 or 4nm) that allows it to be higher clocked.

I really want to see a big improvement on the M2 chip but maybe we’ll have to wait to the M3 or M4 to see a big, not just incremental improvement.

PS: excuse me for being only interested on the low power end of the M chips, and traveling so far in time.
 

matram

macrumors 6502a
Sep 18, 2011
781
416
Sweden
This is a very interesting question, and one of the reasons I’m waiting for the M2 chips on next year devices (iPad Pro and MacBook Air), as I’m pretty sure the M2 will include those A15 efficiency cores.

I don’t know if they are using them on the M1 Pro / Max, maybe that’s the reason they’re including just two of them, but honestly I would bet the architecture is the same as the M1 chip. The same cores, I mean.

We will see how the M2 turns out to be, if it’s a radical improvement based on the A16 architecture, or just a minor update like the A15 at a better litography (3 or 4nm) that allows it to be higher clocked.

I really want to see a big improvement on the M2 chip but maybe we’ll have to wait to the M3 or M4 to see a big, not just incremental improvement.

PS: excuse me for being only interested on the low power end of the M chips, and traveling so far in time.
Seems not, Geekbench results seems to indicate that the performance cores for the Pro/Max are the ones from M1. Seems unlikely that would then change the efficiency cores.

Possibly they were intending to release the new MBPs earlier, but had to wait for parts, and that is why we see this regression.

Personally I will hold out for the second generation I think. But it is taking a real effort NOT to buy now! ;)
 
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Boil

macrumors 68040
Oct 23, 2018
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It sound to me that power consumption and heat dissipation would be such that this would only work in the Mac Pro chassis.

I would expect the full-size Mac Pro to have Dual & Quad SoC options, with the rumored "smaller Mac Pro" (hopefully more of a third-gen Cube; first-gen being the NeXT Cube, second-gen being the G4 Cube) restrained to Single or Dual SoC options...?

I will get a Mac mini when they become available...

Mac mini
  • 10-core CPU (8P/2E)
  • 32-core GPU
  • 16-core Neural Engine
  • 64GB LPDDR5 RAM
  • 1TB NVMe SSD
  • 10Gb Ethernet port
  • (4) USB-C ports
  • (2) USB-A ports
  • HDMI 2.0 port
  • 3.5mm headphone jack
$2999


And I would definitely be interested in a new Mac Pro Cube (but would most likely wait for the M2 Max SoCs)...


Mac Pro Cube
  • 20-core CPU (16P/4E)
  • 64-core GPU
  • 32-core Neural Engine
  • 128GB LPDDR5 RAM
  • 2TB NVMe SSD
  • Dual 10Gb Ethernet ports
  • (6) USB-C ports
  • (4) USB-A ports
  • HDMI 2.0 port
  • 3.5mm headphone jack
$4999
 
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Buntschwalbe

macrumors member
Aug 10, 2021
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Is there a possibility of a small upgrade to the macbook pro lineup next summer to the architecture of the A15? Or will apple wait one year until they upgrade this lineup?
 

Krevnik

macrumors 601
Sep 8, 2003
4,101
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The only thing I wish it has was 2 more efficiency cores. It just kind of annoys me the M1 has more. Those cores can still come in handy on any computer especially a notebook.
While I agree in principle, there's a couple gotchas that make me think Apple realized that they don't need to be so aggressive on the efficiency cores:
  1. Only threads/queues of "background" QoS currently get assigned to the E cores. While the docs suggest “utility” threads/queues could get put on either, there’s not really good evidence that’s the case yet. Everything that is user-initiated or user-interactive will always run on a performance core. An app will never be handling user input on an E core.
  2. Tasks at this QoS level aren’t exactly time dependent. Does it really matter if a background e-mail fetch or spotlight indexing takes a second or two longer? If I do halve the throughput of the E cores, it just means these sort of things might take a little longer. But considering my M1 mini sits with these cores at ~10% load each, two E cores can handle the load just fine.
Here’s the crux of it: macOS doesn’t use the E cores for user work. It uses the E cores to get system tasks out of the way of user work. So at the end of the day, even on the M1, the power benefits don’t come from putting user work on those cores. 3rd party apps can take advantage of this by marking their work with QoS levels, meaning that things like a background “DB cleanup“ in an app like Lightroom is kept out of the way of the things a user opened Lightroom to do.

What this does is let the performance cores “race to sleep” without as many small tasks keeping them awake to handle the growing myriad of things that need attention for the system. It also means there are fewer context switches on the performance cores away from user-initiated work, meaning less overhead to get them done, further improving “race to sleep” and responsiveness of the system as a whole.

When people talk about how snappy the M1 is, I’m suspecting this QoS management is a major contributor to that experience.

On iOS there are APIs for background processing, handing off data fetching to the OS, and more. There’s more opportunities for iOS to mark things as background and be more aggressive about keeping stuff off the performance cores that are available, so there’s very likely a larger benefit for 4 E cores on the iPhone and iPad. On macOS though, the benefit is more limited, but the M1 is fundamentally an iPad chip in origin, and carries the 4 E cores because the iPad Pro needed them and they knew the M1 was going to be used for it, or because they simply wanted to focus on the changes required to bootstrap Apple Silicon on the Mac in the first iteration and dropping to 2 E cores is the result of the data collected from M1.
 
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thingstoponder

macrumors 6502a
Oct 23, 2014
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While I agree in principle, there's a couple gotchas that make me think Apple realized that they don't need to be so aggressive on the efficiency cores:
  1. Only threads/queues of "background" QoS currently get assigned to the E cores. While the docs suggest “utility” threads/queues could get put on either, there’s not really good evidence that’s the case yet. Everything that is user-initiated or user-interactive will always run on a performance core. An app will never be handling user input on an E core.
  2. Tasks at this QoS level aren’t exactly time dependent. Does it really matter if a background e-mail fetch or spotlight indexing takes a second or two longer? If I do halve the throughput of the E cores, it just means these sort of things might take a little longer. But considering my M1 mini sits with these cores at ~10% load each, two E cores can handle the load just fine.
Here’s the crux of it: macOS doesn’t use the E cores for user work. It uses the E cores to get system tasks out of the way of user work. So at the end of the day, even on the M1, the power benefits don’t come from putting user work on those cores. 3rd party apps can take advantage of this by marking their work with QoS levels, meaning that things like a background “DB cleanup“ in an app like Lightroom is kept out of the way of the things a user opened Lightroom to do.

What this does is let the performance cores “race to sleep” without as many small tasks keeping them awake to handle the growing myriad of things that need attention for the system. It also means there are fewer context switches on the performance cores away from user-initiated work, meaning less overhead to get them done, further improving “race to sleep” and responsiveness of the system as a whole.

When people talk about how snappy the M1 is, I’m suspecting this QoS management is a major contributor to that experience.

On iOS there are APIs for background processing, handing off data fetching to the OS, and more. There’s more opportunities for iOS to mark things as background and be more aggressive about keeping stuff off the performance cores that are available, so there’s very likely a larger benefit for 4 E cores on the iPhone and iPad. On macOS though, the benefit is more limited, but the M1 is fundamentally an iPad chip in origin, and carries the 4 E cores because the iPad Pro needed them and they knew the M1 was going to be used for it, or because they simply wanted to focus on the changes required to bootstrap Apple Silicon on the Mac in the first iteration and dropping to 2 E cores is the result of the data collected from M1.
Thank you For the explanation. I wasn’t quite sure what the efficiency cores did but this makes sense. I’ve heard people say that “light tasks” like web browsing are done on the efficiency cores but that never made sense to me as web browsing is not a light task and you want it done as quickly as possible. I would assume any user facing UI task is done on the performance cores, even on iOS. Is that correct?
 

Krevnik

macrumors 601
Sep 8, 2003
4,101
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Thank you For the explanation. I wasn’t quite sure what the efficiency cores did but this makes sense. I’ve heard people say that “light tasks” like web browsing are done on the efficiency cores but that never made sense to me as web browsing is not a light task and you want it done as quickly as possible. I would assume any user facing UI task is done on the performance cores, even on iOS. Is that correct?
Correct.

The big difference is that iOS has a larger bucket of things that can be marked as 'background'. On iOS, any CPU time an app gets while not visible is effectively something that can be marked as background QoS by the OS and run on an E core. Background Refresh tasks likely happens entirely on the E cores, I'd wager, along with background download tasks, geofencing, etc.

On macOS, even if an app isn't active, it doesn't mean the work it is doing isn't user-initiated (me kicking off a batch export in Lightroom and then switching to another app). So it needs more cues from the app on if something is really background QoS or not, but it also means there's fewer background level tasks in general.

The 2/4 split on an iPhone is a good balance. Those 2 performance cores are effectively dedicated to whatever you are doing right then and there. The extra efficiency cores mean that more things can happen in the background without impacting the current app. On iPad, split screen will make apps share the cores, but nothing really unusual or bad about that. This becomes less of an issue on a system with 8 performance cores, when most of them are idle except in certain cases as it is, but there are still power wins if you can keep those performance cores idle more often.
 

januarydrive7

macrumors 6502a
Oct 23, 2020
537
578
I think Apple's original plan was:

New A SoC in October
New Mx SoC in November
New Mx Pro/Max SoC in June the following year

But this year, they delayed the MBP to fall.

In June 2022, we might see the laptops get refreshed with the M2 Pro/Max. Then in November, we might see the M3 in a redesigned MBA.

This is why I'm only getting a base 16" right now in case they refresh again in June 2022.
I'd love it, once they move the entire line to AS, if they'd consolidate all new chip updates to a single event that focuses solely on their silicon. This won't happen, but I'd love it.
 
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dgdosen

macrumors 68030
Dec 13, 2003
2,817
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Why would they license Infinity Fabric from AMD? They have their own stuff and it seems to work very well. As to chip interconnect, Apple has patents which are more advanced that the tech AMD currently uses (Apple's interconnect patents are roughly comparable to Intel's "compute tiles" coming with Meteor Lake). AMD currently connects multiple chips by rooting the signals though the interposer and via a shared interface chip. Apple and Intel are connecting the chips directly via bridges.
What about leveraging TSMC's "3DFabric" along with Apple's own engineering? I'm sure TSMC would love to tout their ability to work in 3D with their flagship customer.

In past posts - @cmaier noted the TSMC reticle size was ~ 858mm^2. AnandTech is noting the M1 Max is 432mm^2 (19.96 x 21.66). Wouldn't it be tough to squeeze in a Jade 2C-Die, let alone a Jade 4C-Die?

Might that point to layers?
 
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Boil

macrumors 68040
Oct 23, 2018
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The larger the die, the less chips on a wafer...

The larger the die, the larger chance of failed chips...

A wafer costs what it costs, no matter how many dies it can yield; so larger dies with a higher failure rate lead to some very expensive bits of silicon...

And for those wanting to stack these SoCs, where does the heat go with a stacked design...?
 

deconstruct60

macrumors G5
Mar 10, 2009
12,493
4,053
Are you guys saying that Jade 2C and 4C will be 2 or 4 discrete SoC with an interconnect?

If Apple was will to go to a much bigger die they could do Jade2C as monolithic ( GPU / SLC / LPDDR5 'stacking' just like from. Jade-chop (Pro) to Jade ( Mac) so would end up with a 64 GPU core cluster that would wrap the rest of SoC around). But that Jade4C would be a chiplet/tile combo of two Jade2C dies.

The die would pragmatically end up more expensive, but could eek out better performance/watt due to only having one die-to-die interconnect rather than 4 ( actually 12 if have point-to-point direct links to each of the other 3 dies.)

The current Max won't work for dense packed 4 tile set up ( even if it did have interconnect which it doesn't appear to have at all). The placement of the RAM connections is wrong. Plus would need a mirror die.


So either.
[J-MA][J-MB]
[J-MB][J-MA]

or
[J2C][J2C]




Sorry not an expert, but how would you handle memory coherency between SoC if the memory is distributed on four SoC.

If use advanced 2.5D or 3D packaging you can put a silicon die under these. 2 or 4 dies just under where they meet.
That would essentially give them a relatively lower power crossbar path between the chip.

IF have a humongous Jade2C monolithic chip there are likely multiple hops communication paths already inside the die. Jumping a minimized distance to another isn't going to be that much different. Similar if connect the 4 dies at the "four corners" where they all meet then have minimized the distance (and power) to connect them.


What would happen with the 3 nm process, would Apple use the same structure and use additional transistors to improve existing blocks rather than adding more cores?

Probably.

macOS caps out at 64 threads .
 

thingstoponder

macrumors 6502a
Oct 23, 2014
916
1,100
I'd love it, once they move the entire line to AS, if they'd consolidate all new chip updates to a single event that focuses solely on their silicon. This won't happen, but I'd love it.
Not really possible unfortunately. Smaller chips get new process nodes first. There’s a reason we’re just seeing these giant 5nm chips.

What I would like to see going forward is Macs with the same chip getting updated in quick succession. It would suck if we he to wait 6 months after a new chip for the 24” to get updated like it was the first time. If we could see all M2 Macs getting updated in a 2-3 month span that’s would be great.
 

GubbyMan

macrumors 6502
Apr 3, 2011
448
2,095
The current Max won't work for dense packed 4 tile set up ( even if it did have interconnect which it doesn't appear to have at all). The placement of the RAM connections is wrong. Plus would need a mirror die.
Would it be possible if they pack them so you have one chip on either side of the board? Basically “3D stacking” them so you have four chips only taking up the 2D area of two. I don’t know much about this, just asking a probably stupid question here.
 

leman

macrumors Core
Oct 14, 2008
19,521
19,679
The current Max won't work for dense packed 4 tile set up ( even if it did have interconnect which it doesn't appear to have at all). The placement of the RAM connections is wrong.

How do you know that? Did you see any die shots?

macOS caps out at 64 threads .

It’s a kernel implementation detail that can easily be changed. Or one can also go Windows way and use CPU affinity groups.
 

Krevnik

macrumors 601
Sep 8, 2003
4,101
1,312
I think the surprise is that the CPU complex is capable of 200GB/s. While they weren’t able to get the GPU complex pushing more than 90GB/s. I would have expected that to be reversed.
 

nquinn

macrumors 6502a
Jun 25, 2020
829
621
I think the surprise is that the CPU complex is capable of 200GB/s. While they weren’t able to get the GPU complex pushing more than 90GB/s. I would have expected that to be reversed.
Agree.

It looks like the MAX chip can offer a little bit of an advantage at 400GB/s since beyond 4 cores and with efficiency cores running the chip can hit around 220-240GB/s, but that's in pretty extreme conditions and only 10-20% higher.


Still kind of glad I bought the 24core gpu MAX variant, but it probably wasn't worth the +$180
 
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