Power curve and efficiency of Apple N3

[leman]

Neat, thanks @theorist9!

I’m wondering, can you also do similar analysis for A15 data and see if it predicts M2 values? I’m curious if you’ll also get a much steeper relationship like what I got here https://mr-mobster.github.io/AppleSiliconPowerTest/analysis.html

 

[theorist9]

Neat, thanks @theorist9!

I’m wondering, can you also do similar analysis for A15 data and see if it predicts M2 values? I’m curious if you’ll also get a much steeper relationship like what I got here https://mr-mobster.github.io/AppleSiliconPowerTest/analysis.html

Sure, I'll get to that when I can. Your current curve fits the data well, and I imagine mine will look very similar.

I might not repeat the scaling-regime breakdown I did for the A17, since that was very time-consuming, and instead do single-function fits (though it would be interesting to see if the scaling exponents on the A15 and A17 are similar).

 

[caribbeanblue]

View attachment 2282989

This graph suggests that the M2 draw 40W to hit 5GHz, while the comparison graph in the GitHub page suggests ~23W?

 

[caribbeanblue]

The A17 is in all respects superior (see below).

Because he gathered data points at various frequencies. The A17 is in all cases more efficient at a given clock. That is, for any frequency X, the A17 will use less energy than an A16.

IIRC, it will also do slightly more work as it has a very modest (small single-digit) IPC gain iso-clock.

I think the original post said that the A17 uses "significantly more power" at usual operating frequencies than the A16 but I fail to see where in the graph this is happening? Am I missing something?

 

[leman]

This graph suggests that the M2 draw 40W to hit 5GHz, while the comparison graph in the GitHub page suggests ~23W?

The analysis on GitHub has been updated to use constrained regression with only non-negative polynomial coefficients, which is likely a better model. If anything, one should be very careful with the interpretations here — one can draw multiple curves that will seemingly fit the data well but wildly differ in their behaviour. What's important to me is that under pretty much any analysis the A17 appears to indicate a flatter curve (with less acceleration as we move to the right), which might be indicative of an architecture that targets higher frequencies.

 

[Confused-User]

I think the original post said that the A17 uses "significantly more power" at usual operating frequencies than the A16 but I fail to see where in the graph this is happening? Am I missing something?

Yes.

The A17's usual operating frequency is higher than for the A16, so this isn't a comparison that teaches us anything, except that Apple clearly believes that running the SoC a little faster/hotter/higher-power is a good tradeoff. If you read the rest of the points Leman makes in that post, you get a much better understanding of the A17's apparent design goals.

Edit to add: To be fair, it's a bit hard to see in that chart, especially if you have trouble distinguishing between the blue and green dots. And the chart doesn't tell you where the chips spend most of their time in the real world. For that you need more info.

 

[headlessmike]

Yes.

The A17's usual operating frequency is higher than for the A16, so this isn't a comparison that teaches us anything, except that Apple clearly believes that running the SoC a little faster/hotter/higher-power is a good tradeoff. If you read the rest of the points Leman makes in that post, you get a much better understanding of the A17's apparent design goals.

Edit to add: To be fair, it's a bit hard to see in that chart, especially if you have trouble distinguishing between the blue and green dots. And the chart doesn't tell you where the chips spend most of their time in the real world. For that you need more info.

To add to this. If the A17 gets things done faster, then it can still save energy by being able to clock down again sooner. Apple has had this approach for years now with their SoCs of offering high performance (and power draw) in bursts with the goal of returning to idle as soon as possible.

 

[caribbeanblue]

Yes.

The A17's usual operating frequency is higher than for the A16, so this isn't a comparison that teaches us anything, except that Apple clearly believes that running the SoC a little faster/hotter/higher-power is a good tradeoff. If you read the rest of the points Leman makes in that post, you get a much better understanding of the A17's apparent design goals.

Edit to add: To be fair, it's a bit hard to see in that chart, especially if you have trouble distinguishing between the blue and green dots. And the chart doesn't tell you where the chips spend most of their time in the real world. For that you need more info.

Are you saying here that the A17 clocks higher for usual daily tasks than A16? But why would it do that if it has a higher IPC?
In any case, in the graph we're both seeing that the A17 is more power efficient at any given clock speed than the A16, and only in the high end of the power curve does the A17 start being less efficient than the A16, which contradicts the claim that the A17 "uses significantly more power at usual operational frequencies" (in the original post).

 

[leman]

Are you saying here that the A17 clocks higher for usual daily tasks than A16? But why would it do that if it has a higher IPC?
In any case, in the graph we're both seeing that the A17 is more power efficient at any given clock speed than the A16, and only in the high end of the power curve does the A17 start being less efficient than the A16, which contradicts the claim that the A17 "uses significantly more power at usual operational frequencies" (in the original post).

Here is a distribution of power draw by processor

As you can see, across all the samples the A17 Pro uses around 0.5 watt more on average. While A17 Pro seems to use a bit less power than A16 when running at the same frequency, it usually runs at higher frequencies than A16 (although it also throttles it's frequency faster). For my test, there is no difference in IPC (but my test is very dumb and does not reflect any real-world workload).

To better evaluate the IPC differences we need detailed samples or CPU counters during benchmark runs. Results alone are not enough, as we don't know the actual frequency of the CPU running the task. In my stress test for example the A17 will reduce its frequency to 3.5-3.6Ghz after just 10 seconds of operation — that's an almost 10% reduction. The peak frequency of 3.77Ghz is only reached for a very brief period of time. A16 instead seems to operate within 5% of the max frequency range for much longer.

The point is that comparing the IPC based on the peak frequency of the chip is likely to underestimate the actual IPC improvements in the A17 Pro.

 

[goldpin]

Here is a distribution of power draw by processor

View attachment 2289136

As you can see, across all the samples the A17 Pro uses around 0.5 watt more on average. While A17 Pro seems to use a bit less power than A16 when running at the same frequency, it usually runs at higher frequencies than A16 (although it also throttles it's frequency faster). For my test, there is no difference in IPC (but my test is very dumb and does not reflect any real-world workload).

To better evaluate the IPC differences we need detailed samples or CPU counters during benchmark runs. Results alone are not enough, as we don't know the actual frequency of the CPU running the task. In my stress test for example the A17 will reduce its frequency to 3.5-3.6Ghz after just 10 seconds of operation — that's an almost 10% reduction. The peak frequency of 3.77Ghz is only reached for a very brief period of time. A16 instead seems to operate within 5% of the max frequency range for much longer.

The point is that comparing the IPC based on the peak frequency of the chip is likely to underestimate the actual IPC improvements in the A17 Pro.

Leman, thanks for producing these power distribution plots, it really helps drive home that a single number on many metrics doesn't tell the whole story of how a complex system with it's own internal control laws operates.

Are Multi core power distributions for the M1 and M2 not available from your code or just not interesting in the context of this phone SoC discussion?

 

[leman]

Leman, thanks for producing these power distribution plots, it really helps drive home that a single number on many metrics doesn't tell the whole story of how a complex system with it's own internal control laws operates.

Yes, we really ought to move away from point estimates to distributions. Single scores are too easy to misinterpret.

Are Multi core power distributions for the M1 and M2 not available from your code or just not interesting in the context of this phone SoC discussion?

They are available, but this also includes processors like M1 and M2 Ultra, which as you can imagine consume much more power and will make the graph unreadable. Still, in case you are curious here is the graph for M1 and M2 machines. Since I am lumping all members of an M-series family together the distribution is multimodal, but it should be easy enough to see which peak corresponds to which model (so far I only have Max and Ultra in there)

 

[dgdosen]

If one were to extrapolate A17 to M3 - where does one think M3 will show up on the "Power Curve by Device" graph?

 

[goldpin]

Yes, we really ought to move away from point estimates to distributions. Single scores are too easy to misinterpret.



They are available, but this also includes processors like M1 and M2 Ultra, which as you can imagine consume much more power and will make the graph unreadable. Still, in case you are curious here is the graph for M1 and M2 machines. Since I am lumping all members of an M-series family together the distribution is multimodal, but it should be easy enough to see which peak corresponds to which model (so far I only have Max and Ultra in there)

Eventually there will be enough AS members the "whole family" plot might be interesting. If the vertical axis were log, would the A-series chips still be discernible while keeping the Max and Ultra on the same plot?

 

[leman]

Eventually there will be enough AS members the "whole family" plot might be interesting. If the vertical axis were log, would the A-series chips still be discernible while keeping the Max and Ultra on the same plot?

Here you go

 

[Xiao_Xi]

@leman Do you have a reason to use a violin plot instead of a box plot? Wasn't there a better description for the x-axis?

 

[leman]

@leman Do you have a reason to use a violin plot instead of a box plot?

Violin plots are much more informative. I would only consider using a box plot if I am 100% certain that ai am dealing with a normal distribution.

Wasn't there a better description for the x-axis?

I’m sure there is. You are welcome to make suggestions and submit pull requests.

P.S. Did Apples new fancy predictive engine just autocorrect “I” to “ai”? 🤪 I mean, it’s not wrong, but…

 

[Analog Kid]

Here you go

View attachment 2289877

Interesting change between A14 and A15-- The earlier generations could have multicore scores below single core. After A15 that pattern changed. Did the OS make a change to force lighter workloads onto a single core at that point? It makes sense to power down the unused regions of silicon...