Those are good questions, and in looking over it in more detail, I was probably too optimistic. You are right to be skeptical.Is that additional PCIe backhaul bandwidth for transported PCIe or for USB 3T?
Also is that a single port controller or two port? ( the picture in the dem room has ne backhaul link coming out of the chip and three other links coming out . Each link is of a different type so that could be representative of just the types or could be that this is a 2 ( or more ) controller . So 2-3 ports only suck up x4 PCIe )
The illustration is not suggestive of an actual PHY chips for a single port. That more so looks like a TB controller than a PHYS chip.
If selling this to Windows PC folks they probably not keen to give up x4 PCie lanes per port. X4 v5 lanes switched down into 2 x4 v4 worth of bandwidth. The rest of press release is about their advances in switch work. Could be the switch inside the TB controller is the tie in.
It may be that all we can say today is that ASMedia is developing USB4 v2 controller chips, and is separately developing PCIe Gen5 bridge technology.
That's different from saying ASMedia is developing an 80 Gb/s USB4 v2 to PCIe 5.0 ×4 controller.
I did some checking, and wasn't able to find a clean test.Did anyone get around to measuring the raw data throughput of Apple’s RDMA TB solution ?