How do the reticle sizes currently compare between N5P and N3? I did some research awhile ago, but couldn’t find much about that in particular. IIRC, M1 Max was pretty close to the N5 reticle limit.
Edit: M1 Max was 432 mm^2 according to Wikipedia, and in August 2020
techradar claimed the DUV and EUV reticle limit was a whopping 858 mm^2. So, maybe not close to the limit after all?
The M1 Max was used to constructed the M1 Ultra. 2 *432 --> 864 is hovering around the reticle limit. The packaging technology Apple used for the M1 Ultra ( Info-LSI) does have a 1x reticle limit. Apple could possible go to a path where they abandon Info-LSI ( the quad die "Extreme/much-bigger-package" is likely to blow far past what Info-LSI can do even with some improvements. ) or a 1.25-1.5x reticle Info-LSI shows up.
Or it could be that much higher clocks (performance ) or much lower power is what the main levers on N3 would be. Going to a "Max-like" die that is 406mm^2 would:
1. allow Apple to stay under the reticle limit for the current Info-LSI packaging. Basically simpler, more cost effective packaging.
2. allow Apple to get more useful dies out of single wafer. Smaller dies have incrementally higher yields. They also by definition just take up less space on the wafer. That would mean they would need less wafers to make more Ultras and Quads. Given Apple is *still* behind on getting Studios out the door having more supply might actually help. N3 wafers also cost more. So more useful dies out of a wafer lowers the per unit cost assigned to each working wafer. Again is works out right saves Apple more money which they can use for bigger margins.
What Apple pays TSMCs for is putting wafers through the fab process. How many working dies come out the other side is not TSMC's problem. You paid for the wafer you get the wafer. If there are 4 or 40 or 400 working dies on the other side that is your (Apple's ) cost problem. Yes, TSMC needs to provide decent yields to get customers to order a reasonable number of wafers to be process. So they care , but the actual costs is falling on the customers. And the customers control how big the dies are. TSMC largely doesn't dictate that to the customers. If customer makes a bigger die, then the yield goes down.
If Apple stays on N5P for a "More cores and more stuff" M2 Max then for a 8% bloat ( 466mm^2 ) they'll get less dies and lower yield out of a N5P wafer than they were getting before. N3 wafers may cost sufficiently more that trade-off is worth it. Or perhaps not.
3. allow Apple to mitigate risks associated with the new tech of N3. N3 has a "Flex Fin" technology that really hasn't been tried in large scale production before by any fab. Implementing a "working" M2 architecture on top of a new fab process would be pretty close to following Intel's old "tick/tock" strategy. Either do large tweak to the microarchitecture or do a large tweak to the fab process , but largely avoid doing both at the same time.
There is lots of hype about the first N3 implementation will lead to some massive leap in core counts or power savings. Perhaps that is much more narrow. No massive core count increases (take same increase as bloating the N5P would give) and the power savings also incremental (as fell out the new technology without overly optimizing to save time. ).
406mm^2 would be in reach if just waited for N4P (-6%) . A conservative use of N3 (-20%) could take the size down to 346mm^2. That's still 100mm^2 bigger than the current M1 Pro. It would still be a 'mid-size" die, but far closer to the size of chips Apple would likely prefer to make ( more volume out of fewer wafers and better margins. )
And 4 * 346 is 1394mm^2. That is relatively very large, but more tractable than 1864mm^2. Again bigger , more complex packages likely lead to incrementally lower yields (and higher costs... which Apple likely doesn't want to pay.).
As for Apple would never do that.
A10 -- 16nm 125mm^2
A10X -- 10nm 96.4mm^2
Yes , the iPad Pro chip was
smaller than the iPhone chip. And 10nm was also a fab tech inflection point for TSMC.
The M2 Max bloating on N5P would not matter as much if Apple was decoupling the Ultra from using exactly the laptop Max die in the desktops. The Ultra and bigger are never used in a laptop. If Apple stripped the UltraFusion logic and connectors from the die they'd get a smaller die or could swap that area for a few extra E-core or G-core space. Even more so for a M2 Pro since it didn't have the often completely unused ultrafusion connector soaking up space anyway.
So if Apple couples the MBP 14"/16" Max dies to solving the unit volume problems of the Studio and more so the Mac Pro then there is a decent chance the Max could get pulled into N3 because it is a better fit for those desktop systems. ( probably get some decent reduction in power consumption to help the laptop also as somewhat a side effect. )
If Apple decouples the laptop Max die from the desktop issues then N5P could make some sense for M2 Max. M2 Pro doesn't present thermal growth problems since same current systems have a Max to deal with. (and a M2 Pro Mini has gobs of headroom because built for Intel desktop set up. )