Mn Max has to be the best version of the Mn, right? But surely the Mac Pro will have a more powerful processor than any laptop, if only to fit in more RAM, so what are they going to call that one?
The M1 "How much money do you have" and the M1 "if have to ask you can't afford it".
The simplest would be. M1 Max2 and Max4
If basically adding a small addition to the Max chip die to do mainly just do. "inter die" communication then would just have two or four Max chips. "2" and "4" as easy ways that identify that will print nicely on an incrementally bigger package.
Come to think of it, I wonder how they'll handle RAM in the Pro. I mean, you're not going to get a terabyte of RAM on a SOC are you. I wonder if they'll have two layers of RAM: some on the SOC, some external. <shrugs> I have no idea.
The most cost effective path for Apple is .... almost exactly the same way. The floorplan of the Max chip though is off for doing a close packed 4 die layout. Put the chip interconnect at the "top" and move some of the top I/O off to bigger side and that could mate two dies head to head. Have to move the memory I/O to one side and the bottom.
| double RAM | double RAM | |
| double RAM | M-floor-plan-A | M-floor-plan-A-mirror | double RAM |
| double RAM | M-floor-plan-A-mirror | M-foor-plan-A | double RAM |
| double RAM | double RAAM | |
The upper, left. floor-plan A is rotated 180 to be placed in the lower right. Upper right A-mirror is rotated 180 degrees to be placed in the lower right. So all have "bottom" and "side" edges that are meant to abut one another.
I suspect though might just continue on same path as the Pro -> Max transition where add more GPU at the "bottom" (with "extra" video de/encoders removed ) but in a mirror fashion to end up with CPU cores at the other end. But also tweak the old top to add in an interconnect. So an even bigger monolithic for Jade2C. ( up closer to 700mm2) And then just hook two of those together to get to "Jade4C". And just charge lots more money.
| double RAM | double RAM | double RAM | double RAM |
| extender rotate left | M1 Max rotate 90 right | M1 Max rotate 90 left | extender rotate right |
| on bigger die 1 | on bigger die 1 | on bigger die 2 | on bigger 2 |
| double RAM | double RAM | double RAM | double RAM |
each of the two 64 GPU die chunks would be minimized on distance and have relatively short paths to LPDDR5 .
The anandtech article on the M1 Pro and Max described the Max as:
"... Essentially it’s no longer an SoC with an integrated GPU, rather it’s a GPU with an SoC around it. ... "
www.anandtech.com
so if used the core of a 64 GPU core complex as the starting place and wrapped the other SoC elements around that that is close to what you'd get. ( eliminating some redundancies in video en/decode , ML , SSD controller , etc to cut down on the bloat ). Then they'd just interconnect the two dies. That could be lower power between two dies than between four. ( so perf/watt probably better ... which is Apple's holy grail priority. ).
I don't think Apple cares about getting to > 1TB capacity on a M1 iteration. That means they can skip doing a memory controller that does ECC also (and more maximizes reuse across the line up). Even more so if they are shooting for a system that completely dumps PCI-e slots as that second variation likely would to max reuse of the M1 Max die floorplan.
I think folks are missing the forest for a tree ( slotted RAM DIMMs ) . Jade (Jade-chop) , Jade2c , and Jade4c are all the same code name. So the CPU and GPU cores are likely the same across
all of them. It is the same baseline building blocks collected into different die sizes. That's why share the same project name. And that probably extends into the memory controllers also.
