What process node will the M3 chip use?

[JPack]

True, but it's rather strange how marginal the performance gains were compared to A15. Even Apple didn't want to make too many comparisons in their fall event. If it was designed with N4 in mind from the start then more optimizations would be expected. Either that or they are really bumping up against the limits of the 5nm/4nm-class nodes with regards to performance per watt.

There are so many reasons why that could be. Many of them don't include "A16 was designed for N3 but had to backport to N4."

Apple lost their chief architect GWIII in 2019. Cost of N3 wafers deemed was too high. Silicon engineers were busy working on other projects like Mac Pro, VR, Apple Car, 5G baseband, etc.

 

[deconstruct60]

... Therefore, if the M3 is to be based on N3B like you said, it will probably not have the A16 IP we saw (that’s practically identical to that of the A15) but instead the new IP that was delayed.

If the N3B cores are working for the M3 why wouldn't they work equally as well for an A17 ( that was suppose to be A16)? If Apple has a working set of CPU/GPU/NPU/video/Display cores on N3B why are they going to throw them out the window.

If only didn't use them because the timing of N3B was wrong how is N3E anybetter. TSMC has over the long term placed N3E as coming 12 months after N3B. If N3B slides 'late' that is not particularly going to bring N3E forward by a whole lot.

N3 (what now calling N3B) was targeted for years for 2H '22. That was always pragmatically too late for the iPhone. ( which needs to start ramping April-June ... i.e. Q2 not Q3 ). N3E got pulled forward about a quarter and N3B started in Q4 '22 so that is Q3 '23. Still pragmatically too late for the A-series.

N3E doesn't make much sense for Apple. The memory/cache density is exactly the same as the N5 family. [ i.e., the caches won't get any smaller. So if want a bigger cache need a more expensive and larger die.] It would make sense for Apple to just skip N3E and do a N3B -> N3P transition.

N3E isn't design rule compatible with N3B. So if have to 'respin' the whole layout it is far more time and cost efficient just to use the N3B that had working. Waiting for N3P gives time to do the redesign and hopeful could get some small memory/cache reduction with the refinement. The only hang up with be that N3P also landed in the 2H in 2024 ( a bit too late).

For folks who deeply believe in the 'super last minute scramble' of whipping together the N4 A16 , then if Apple is so 'last minute ' behind why wouldn't they use the N3B design they largely had instead of once again tossing it out and starting over. Personally, I don't think the N4 targeted SoC was all that 'last minute'. It was the safer choice( roadmapped in 2020 as available in 1H '22 ... so if some fab scarcity/panademic drama more likely to be available in volume. ). Apple picked something safe... likely not late in the process.


N3B costs more to fabricate ( more complicated layers and takes longer to gestate ) than N3E , but that really probably isn't a 'show stopper' for Apple. They can just charge more (or allocate more of the bill-of-material costs to the A/M-series SoC). And if gestates slower than start a month or two earlier (e.g., March-April , instead of May-June ). 45K/wafers enough is enough to do both bleeding-edge A and leading M series in most 'normal' quarters.
A17 is not the iPhone volume. It is only the iPhone Pro volume. ( a bit more than 50% of the newest iphone model but not anywhere near 50% of iPhone sales. )

Even more so if Apple used Jan-April to build up some stockpiles to smooth out initial demand bubbles for the N3B SoCs. [ Apple generally doesn't like carrying excessive inventories but they are not broke either. ]

 

[deconstruct60]

True, but it's rather strange how marginal the performance gains were compared to A15. Even Apple didn't want to make too many comparisons in their fall event. If it was designed with N4 in mind from the start then more optimizations would be expected.

Really? In the beginning of a pandemic where all your workers are scrambling to do product design under substantially new conditions and equipment. That Taiwan has banned all foreign visitors ( so no .. drop by the factory and talk things out sessions ).

The other issue was that there were no design tools for FinFlex previous to N3 design.


Apple picks subset of the SoC die to tweak. There are two variants of N4. One is zero changes for N5. Two requires some modest design tweaks. It is how Mediatek beat Apple to N4 ( ~ Q1 2022 ) by doing the first with Dimensity 9000 and then 9000+ ~ Q3 2022. And Dimensity 9200 on N4 ~ Q4 2022 .


The M2 is N5P and mainly just a bigger die with more stuff. Nothing earthshattering new there either.

I think businesses are not getting enough credit for still getting product out the door in extremely unusually disruptive conditions.

Either that or they are really bumping up against the limits of the 5nm/4nm-class nodes with regards to performance per watt (i.e. they can't eke out any more performance without making the chip less efficient and decreasing battery life).

It isn't so much that N5/N4 is the 'end of the line' as much as the major node improvement iteration gaps are quite as fast. Some fanboy like to spin the hype that it was all Apple design genius that brought the most of the substantive improvements and the fab process improvements were just a 3rd , 4th , or 5th level contributor.

One, lots of 'low hanging fruit' is all gone in both the design and fabrication advancements. TSMC N2 isn't going to come hyper rapidly or inexpensively.

If Apple spends 2-3 iterations on N3P by the end of that 'squatting' period probably will see another "well not much improved this last iteration" happening again.

 

[sunny5]

A16's GPU architecture is such a failure and that's why Qualcomm outperformed Apple Silicon for the first time in GPU area. I highly doubt that M3 will be A16 based but A17 based. Otherwise, M3 will still have a mediocre A16's GPU performance which isn't really better than M2. Beside, there are plenty of time before M3 released since A17 has to come out in September along with iPhone 15 Pro anyway.

 

[senttoschool]

If H2 2023 = June 2023 and beyond, then I don't see how Apple could use N3E for A17. They'd use N3 for A17. By June, the initial supply for the iPhone 15 will have started production already. They can't start until they have the chips. Usually, Apple begins manufacturing the next iPhone's chips in April ish.

PS. It does look like N3 might be superior to N3E for M3. Yes, the power and performance are slightly worse, but the logic scaling is better and the SRAM is slightly better than N3E.

It'd make sense to make the M3 on N3 and it'd make sense to make the A17 on N3E because it has lower power requirements (if N3E can make it on time for A17).

 

[dgdosen]

Is there any news about other customers using N3B?

 

[Boil]

Is there any news about other customers using N3B?

The rumors are that Intel backed out of N3B and that Apple has all N3B allocation to themselves...?

 

[dgdosen]

The rumors are that Intel backed out of N3B and that Apple has all N3B allocation to themselves...?

Yep, we knew that. As time moves forward and Apple fulfills its commitment to N3B wafers, we can speculate on what happens next. If TSMC has no other N3B takers, it's either discount to Apple or let that multi-billion $ investment sit idle. It becomes a variable-cost-only decision for both companies. It'll be worth it from TSMCs long term position to sell at a loss.

The results of that negotiation will be interesting to know.

 

[senttoschool]

Yep, we knew that. As time moves forward and Apple fulfills its commitment to N3B wafers, we can speculate on what happens next. If TSMC has no other N3B takers, it's either discount to Apple or let that multi-billion $ investment sit idle. It becomes a variable-cost-only decision for both companies. It'll be worth it from TSMCs long term position to sell at a loss.

The results of that negotiation will be interesting to know.

At TSMC’s size, they probably have contracts for N3 wafers agreed upon years in advance. You can’t invest tens of billions into a node without these agreements in place.

So if Intel backed out, they probably had to pay steep fines - enough to make N3 still profitable this year or until the next customer is scheduled to use N3 based on contracts.

 

[prime17569]

This article claims that A17 will be manufactured on N3B, and that TSMC is struggling with yield. (The source the article cites also claims that A17 performance targets have been reduced due to manufacturing variability.)

If true (emphasis on if), then it is probably a given that M3 will be manufactured on N4, possibly N4P, and based on A16 IP. Given the limited amount of N3B wafers available, Apple would want to preserve them for their highest volume products (i.e. the iPhone).

Apple A17 Bionic SoC Performance Targets Could be Lowered

Apple's engineering team is rumored to be adjusting performance targets set for its next generation mobile SoC - the A17 Bionic - due to issues at the TSMC foundry. The cutting edge 3 nm process is proving difficult to handle, according to industry tipsters on Twitter. The leaks point to the A17...

www.techpowerup.com

Here is my speculation: N3B would make sense for a next-generation Apple chip, considering its higher cache density than even N3E and that Apple's designs have traditionally been cache-heavy in order to increase performance. However, according to TSMC, N3B has no migration path to future N3 nodes such as N3E, so it will probably be a headache for Apple engineers to migrate to N3E from N3B. Apple engineers might choose to stick with N3B for 2-3 years until N2 nodes are available (TSMC says that volume production will likely begin in 2025 or 2026). Note that all of this speculation only holds if the above article is correct about A17 being based on N3B rather than N3E.

 

[dgdosen]

At TSMC’s size, they probably have contracts for N3 wafers agreed upon years in advance. You can’t invest tens of billions into a node without these agreements in place.

So if Intel backed out, they probably had to pay steep fines - enough to make N3 still profitable this year or until the next customer is scheduled to use N3 based on contracts.

I agree with Intel paying fines for punting on N3B after paying a premium to get in , but that's orthogonal to the current situation. Idle or discount or ???.

It may not make a difference to financial reporting, but it would to cash flow, and cash is king...

 

[deconstruct60]

How is it known that A17 will be on N3E exactly? ...

Apple to use TSMC's next 3-nm chip tech in iPhones, Macs next year

Move will mark industry's first adoption of updated production technology

asia.nikkei.com

This part of the article makes little sense logistically.

" ... The A17 mobile processor currently under development will be mass-produced using TSMC's N3E chipmaking tech, expected to be available in the second half of next year, according to three people familiar with the matter. ... "

If TSMC N3E is only available in the 2H '23 then how is it suitable for the A17 which has to start production in the 1H '23? The only way N3E would be viable would be if the A17 was NOT going to ship in Q3 '23 ( i.e., September like normal) and time shifted to something like late October - mid November. Apple could if they wanted to, but why would they? ( all the other newest fancy features are herded into the "Pro" model along with the A17 to crank up the average selling price. Pretty likely would end up with same situations as Fall '22 were the Pro model sales never 'caught up' to the initial demand bubble until after Christmas buying season was over. )

Apple has consistently picked a process for the 'new' , Fall iPhone SoC there was already in HVM status at least in the 1H of the target year (if not earlier).

These SoCs are not like making microwave popcorn. It takes more than several weeks to make a SoC die of either flavor of N3 . (N3B longer than N3E , but both take substantial amount of time). Complicating that further is that the first 1-2.5 months of a new iPhone is a large 'demand bubble' that far outstrips the normal production pace Apple would need for the SoC. So start 2-3 months early so that can building inventory so can keep up with unusually high demand. So need to be seriously building stuff in May-June to have that necessary lead time. 2H is July; at best.


Much of this odd ball logistics stuff occurred last year this time also why there were hand waving reports of A16 coming on N3 ... which again made zero pragmatic sense when TSMC estimates for several previous years to that said that N3 wasn't coming until 2H '22 ( also missing the 1H deadline to start production lead time for the September iPhones).

TSMC has at several points said N3E was scheduled to be about 12 months after N3. So if N3 was going to 'miss' in '22 then N3E is going to do the same thing in '23. N3 (now N3B) was always a far more viable "HVM status active in 1H '23 for iPhone ramp in Q2 " fab process for the last several years. In very late '22 , TSMC said N3E was being pulled forward a 'quarter' by TSMC but if had been targeting mid-2H '23 that only pragmatically pulls the new start to around the Q3 transition.


Pretty good chance the M3 and A17 share the same basic core cluster building blocks ( P core cluster, E core cluster , GPU cluster group, etc. ). Long time ago the M3 probably was going to target end of '22 to 1H '23 to come out for the Mac line up. It is unlikely there is no huge deep technical need to do the Axx first and then do the Mx second when they share much all the same subcomponent building blocks. There are some 'uncore' differences but one is a bigger die which as different number of 'building blocks" than the other. Making the bigger chip first is totally is charge proportionally more money for it. ( either a small/cheap or a large/expensive die can be used as a 'pipe cleaner' for a new process. The A10X 10nm June 2017 predated the A11 10nm Sept 2017 and jumped fab node over A10 16nm Sept 2016 . Even Apple has not dogmatically always done 'smallest die first on new node'. ) .

The iPhone having a 'fixed in stone' release date of September means periodically it is going to miss fab node updates ( which do NOT come on exact 12 month intervals. Likely going to even less so going forward as "smaller" gets "harder" . ).

 

[deconstruct60]

View attachment 2177194

If H2 2023 = June 2023 and beyond,

Technically no. H2 2023 = July 2023 and beyond . Not June. June in in Q2 which is less than 'half'. 2H = Q3+Q4 . Apple could order up wafers that were technically in the 'at risk' status still in June. But yeah even if they stretch the start time late-May-to-early-June it is still dubious timing if trying to hit a September deadline.

then I don't see how Apple could use N3E for A17. They'd use N3 for A17. By June, the initial supply for the iPhone 15 will have started production already. They can't start until they have the chips. Usually, Apple begins manufacturing the next iPhone's chips in April ish.

April-ish was a bigger factor when both the new 'plain' iPhone and iPhone Pro were both on the same SoC.
Mostly like the new 'plain' iPhone is going be on A16 . The Pro over the last year or so is selling more than the 'plain' but it is substantially less than half of all iPhone production. If Apple cranked up the price of the Pro that might shrink demand (even with the An+1 SoC in it as a selling point). In short, the smaller the initial demand bubble , then the smaller the necessary lead time to build inventories.

Apple could do N3E is there was some 'show stopper reason' , but likely just would not hit normal rigid deadline for the iPhone. The world wouldn't end of the iPhone Pro didn't come out until October or a little later. Financially, for Apple though it would be a problem (over the short term).

The 'show stopper' probably wouldn't be in that chart though. It would likely more so be cost and/or 'bake time'. If N3B was a A17 margin killer on price , Apple might skip it. It wouldn't have to do with performance or battery... mainly a Scrooge McDuck issue. They would hope to time shift the iPhone Pro sales with any delay that money saving move would cost them. ( some other companies design teams are skipping N3B because don't have the 'luxury' of charging more. They are starting on N3E in part because it is more affordable both in design and wafer costs. )

More likely though Apple would just pass along more expensive A17 costs to end users and just use N3B. ( And may just skip it as a trickle down to cheaper Apple products like the 'plain' iPad over time. )

PS. It does look like N3 might be superior to N3E for M3. Yes, the power and performance are slightly worse, but the logic scaling is better and the SRAM is slightly better than N3E.

The farther up the M3 generation die size you go the more cache/SRAM going to have. It isn't just the M3. There is probably at least a M3 Pro , if not a M3 Max in the mix.

The A17 probably minimizes the SRAM size exposure . ( the watch SoCs would have even smaller SRAM exposure , but they seem to be in fab process progress molasses ... so not hitting N3-family any time soon or intermediate time frame)

It'd make sense to make the M3 on N3 and it'd make sense to make the A17 on N3E because it has lower power requirements (if N3E can make it on time for A17).

If in 2024 Apple wanted to cover the new 'plain' iPhone and the iPhone SE in the A17 then N3E would make sense also. it is less expensive and can produce the dies faster. If they want to use it as a 'trickle down' the product stack chip it makes sense if take a multiple year perspective. Starting that multiple year run 2-3 months late may be worth the short term hit.

Going from 'already working' N3B cores to N3E cores would cost substantial money and time even if did't change the design much. N3B and N3E are not design rule compatible. For Apple to go to N3E there likely would need to be some substantively money saving issue involved. The power gap just isn't that big.

 

[deconstruct60]

This article claims that A17 will be manufactured on N3B, and that TSMC is struggling with yield. (The source the article cites also claims that A17 performance targets have been reduced due to manufacturing variability.)

from article

" ... the A17 Bionic's overall performance goals being lowered by 20%, mainly due to the TSMC N3B node not meeting production targets. The factory is apparently lowering its yield and execution targets due to ongoing problems with FinFET limitations. ..."

Errr N3E is just as FinFet as N3B is. So if FinFET is the root cause problem here... N3E wouldn't change much.

The bigger issue is more likely that N3B is using more multipatterning than N3E does ( i.e., FinFET isn't the core root cause issue here).

And "overall performance goals" set when ? Before FinFlex design tools were completely validated? If the goals were set way too unrealistically high then sliding 'back' 20% isn't necessarily a 'bad' thing. On TSMC charts N5->N3 for several years that was never suppose to be a well over 20% performance increase (10-15%). Were some "ultra revolutionary high" goals even tractable in the first place ? Dropping 20% could just mean just stopped drinking the kool-aid.

If true (emphasis on if), then it is probably a given that M3 will be manufactured on N4, possibly N4P, and based on A16 IP. Given the limited amount of N3B wafers available, Apple would want to preserve them for their highest volume products (i.e. the iPhone).

That doesn't make N4/N4P for M3 more probable. If Apple had a long term plan to put M3 and A17 together then it is probably still on track.

The article is a bit whacked. "Struggling with yield" probably is being oversold here unless one of Apple's objectives in this generation was maximum overlocking the fab processes baseline target. (probably not).

again from the article
"...The leakers have recently revealed more up-to-date A17 Bionic's Geekbench 6 scores, with single thread performance at 3019, and multi-thread at 7860 ..."

First, there is not good reason why though GB6 numbers would not already reflect the supposed 20% reduction. Second, the A16 is turning in ST 2500 and MT 6400 GB 6 scores. Oh the 'horror' of just being 20% or 23% faster scores than previous gen. Yeah that is a "show stopper problem" ... *cough* not.


There has been some folks caught up in the hype train of ...

"... Various publications have been hyping the mobile SoC's single thread performance as matching that of desktop CPUs from Intel and AMD, more specifically 13th-gen Core i7 and 'high-end' Ryzen models. Naturally the A17 Bionic cannot compete with these CPUs in terms of multi-thread performance. ..."

the meme that Apple has to try to claim the ST drag racing crown to have an interesting enough M3 generation. That is mainly just a hype train. N4 isn't really going to help Apple claim some drag racing crown substantially much better than N3B would. N3B would give Apple the option of either making the M3 generation die sizes a more reasonable. After M2 generation bloated up. Or Apple add substantive new features ( e.g., the hardware RT that another faction is clamoring for ). N4 isn't going to bring along hw RT any better than N5P did (not really any substantive transistor budget increase. )

The A16 is on N4 and it gets whipped by the N3B A17... why would the M3 dies pass that up to say on N4????????



For the Ultra (and above ) multiple chip solutions N4 does even less. There are bigger die size limitation issues there where the M2 die size bloat is more acute. Apple needs to pull the die sizes back and N4 only has a very limited impact there. ( if have to bloat N4 sizes even bigger that won't necessarily increase yield either. )

Apple A17 Bionic SoC Performance Targets Could be Lowered

Apple's engineering team is rumored to be adjusting performance targets set for its next generation mobile SoC - the A17 Bionic - due to issues at the TSMC foundry. The cutting edge 3 nm process is proving difficult to handle, according to industry tipsters on Twitter. The leaks point to the A17...

www.techpowerup.com

Here is my speculation: N3B would make sense for a next-generation Apple chip, considering its higher cache density than even N3E and that Apple's designs have traditionally been cache-heavy in order to increase performance.

Cache destiny for the rest of N3 family probably isn't going to get any better. N3B is likely going to be about as 'good' as it gets. ( a bit of a dual edged sword in that higher costs , slower 'bake'/gestation times come with that also).

Apple is likely one of the primary customers who asked for the cache density targets of N3B in the first place.

They also do not necessarily need to keep just completely monolithic dies as they more along in N3-family. 3D cache or different core/cache disaggregation can split the bulky cache into a bigger, seperate die that just have to glue back together to form a whole.

However, according to TSMC, N3B has no migration path to future N3 nodes such as N3E, so it will probably be a headache for Apple engineers to migrate to N3E from N3B.

It would for more so be 'work' than a headache. It would cost time to switch to N3E. If have N3B bugs to fix anyway, then it would be better to fix the N3B bugs in a deliberate fashion, than doing some rush job so that can completely respin the M3 for 2023. If timing lines up with rollouts, then can skip redesign work until get to N3P (which should have more improvements than N3E). Or push some N3E rework into a 2024 rollout.

The issue is that Apple has a finite number of silicon designers/developers. Spread too thin and that will likely cause problems of its own. Apple extremely likely has the talent to move from N3B to N3E/P . They don't have to 'hide' from work. The key factor is not overloading them chasing after doing everything for everybody. ( hyper modular everything socket focused SoC , the single thread drag race killer . the x090 'killer' GPU , the maximum core count 'killer', etc , etc. )

Apple engineers might choose to stick with N3B for 2-3 years until N2 nodes are available (TSMC says that volume production will likely begin in 2025 or 2026).

Probably not. N3P if available in 1H '24 would be good target for A18 or A19 if 2H '24. M4 coupled to that some timing wise ( not the full line up... plain/Pro/maybe-Max ) . N2 is an even bigger radical design change (and cache shrink issue may not be cleared up on first iteration of that either.)

Note that all of this speculation only holds if the above article is correct about A17 being based on N3B rather than N3E.

If Apple is leaning 'too heavily' on FinFlex for N3E as well ... that whole "overly optimistic projections due to low real experience and limited tool maturity" could just as equally in effect. N3E is probably not a panacea on the new learning curve issues. Probably less bumpy road, but also issues.