Where are those 3nm Apple Silicon products?

[Gudi]

Isn't it ironic that high demand for phones turns them into a fashion product, which must be available for the season − whereas desktop PCs don't get refreshed until new chips are available? On one hand all the R&D money goes into mobile, on the other hand mobile can't even wait for the innovations to be completed.

 

[Longplays]

Would this be the first time Apple has used two different SoCs for one product?

I think previous iPhones had different gen iPhone chips just recently.

It may be a cost cutting measure, SoC yield issue or they've hit a sweet spot for their economies of scale in light of lengthening replacement cycle of users.

Since the 90s the typical mobile phone replacement cycle was 2 years.

About a decade ago it lengthened to 3 years or more as smartphones have reached a point that they were "good enough".

Hence iPhone product design changes switched from every 2 years to every 3 years.

If batteries were user replaceable and other parts were easily repaired then it may start approaching 4-6 years like a computer.

 

[theorist9]

Does it make any sense?
View attachment 2216369

Apple’s A17 Bionic Could Switch To TSMC’s N3E Process In 2024 For A Lower Production Cost, But It Will Come At A Drawback

One rumor claims that the A17 Bionic for the iPhone 15 Pro models will switch to N3E process from TSMC starting next year

wccftech.com

Yes. Given the reports of low-yielding N3B, it's unlikely Apple designed A17 to push the limits of that process. Apple knows they need millions of chips. Apple can lower their target clock, say from 3.65 GHz to 3.5 GHz to make A17 suitable for N3B and E.

It only makes sense to use expensive and low-yielding N3B for iPhone. Everybody knows September is iPhone month. But everything else including Mac and iPad doesn't have an expected date. Those can wait until early 2024 for chips fabbed on N3E.

I don't see how that makes sense. N3E is expected to be higher-performing than N3B. It's less expensive because TSMC figured out a way to simplify the fabrication process (fewer metal mask layers, IIRC), not because it's lower-end. Thus why would there be a performance loss in switching from N3B to N3E?

 

[JPack]

I don't see how that makes sense. N3E is expected to be higher-performing than N3B. It's less expensive because TSMC figured out a way to simplify the fabrication process (fewer metal mask layers, IIRC), not because it's lower-end. Thus why would there be a performance loss in switching from N3B to N3E?

N3E offers better clock than N3B but lower logic and SRAM density. When A17 rolls around for regular iPhone 16, SE, iPad, and Apple TV, I suspect Apple will constrain the die size meaning less SRAM.

 

[deconstruct60]

Does it make any sense?
View attachment 2216369

Apple’s A17 Bionic Could Switch To TSMC’s N3E Process In 2024 For A Lower Production Cost, But It Will Come At A Drawback

One rumor claims that the A17 Bionic for the iPhone 15 Pro models will switch to N3E process from TSMC starting next year

wccftech.com

Maybe. I'm not sure that Apple would call it 'A17' if they moved it to N3E. N3B and N3E do not use compatibile design rules. Apple would have to a substantive redesign of the whole implementation. ( not a 'from scratch' redesign, but likely a substantife 'reflow' and signficant 'floorplan' changes ). It isn't 'cheap' to do. Different enough that could slap a different number on the package (e.g., call it A18 ).

If N3B is still getting incremental yield increases through 2024 then it may not make sense at all. One report said that TSMC could be getting some new equipment to make the multipatterning they are doing for the extreme small options of N3B better. N3E's SRAM/cache is bigger (old N5 size). N3B is slightly smaller. But Apple uses higher than average amounts of cache. So likely some die size bloat. If you make the die size bigger then the N3E yield goes very incrementally down.


N3E also gives up on the densest FinFlex option. If Apple made substantive use of that option (e.g., 10% of the die ) then that part of the die would bloat up also. Again impacting costs and yield. It think the main customer who was asking for the 'crazy high' density FinFlex option was Apple. That would make lots of sense since they are the only ones who stuck around. unless that very specific features is causing most of the yield problems ( defect density is much higher in those zones ) , Apple may not want to give it up.

In 2024 is the yield gap between N3B and N3E still going to be huge????? That is the critical question. There is lots of hype that N3B is just inherently doomed on yield. I'm not sure those are really well grounded. N3B has a problem that the 'bake time' is much longer than N5 family bake times. That means the feedback loop on discovering issues and feeding corrections back through the production cycle are longer. So the process of "pipe cleaning' (learning more as process wafers and feeding that back through to new wafers ) is going to be slower , but not necessarily 'broken' in that cannot eventually get the information back to new, clean wafer starts.

N3E is also longer bake time than N5 family. It is getting a little bit of a boost because some N3B quality improvements are coming back through it. But both N3B and N3E are getting those; just at different times.

What makes the 'pipe cleaning' on N3B worse is that everyone dropped out the early going except for Apple. Another report had some deal worked out between Apple and TSMC so that Apple doesn't pay for 'bad dies' until hit something like 70% mark. That is a good 'Scrooge McDuck' move for Apple, but is sure as shooting isn't going to make the pipe cleaning process go faster!!!! TSMC doesn't want to eat all of those 'bad dies' while Apple makes 100% clean profit on the good ones. [ Digitimes might have been on to something when the capacity usage rate back in Feb-March was way below 50%. A bunch of idle machines because TSMC doesn't want to loose money at a faster rate. ]. Once again ... slower feedback cycle doesn't necessarily means 'bad' yields once have collected enough information (and tried various 'fixes' ).

That is why multiple early adopters help. It spreads out the risk costs over multiple organization who collectively each have to 'eat' more of the early pipe cleaining process overhead. Apple freaked out about risk costs could mean the process is going slower.

However, if Apple is making TSMC eat a mountain of bad dies .... I can't see how Apple then quickly jumps off N3B. At some point TSMC is going to looking to recover most of the loss eating cost. Decent chance that deal says "TSMC eats the early costs and Apple does 2 years on the process. "





Apple doing A17 on both N3B and N3E is somewhat close to when they ran the same base design through both TSMC and Samsung. That is pretty close to what would be needed. So it has basically been done (but in parallel , not serially).



P.S. this really could be about something other than the iPhones. Usually Apple uses the top iPhone chip in other products, AppleTV, entry/bargain iPad , iPhoneSE. If Apple is going to need A17 chips in 2025-26 timeframe then N3E would make lots more sense. If Apple is the only volume player on N3B and then more 75% of their volume to something else ... then there is no volume left. N3B is not a long term node and Apple's relatively long term plans to use it creates a conflict. That really is NOT about the iPhone though. Nor is it about N3B's yields are always going to be 'bad'. The yield can be eventually good and no one uses it. (super slow bake times and wafer price )

 

[MayaUser]

indeed, probably yes

 

[Xiao_Xi]

Which node does Mediatek use for the SoC: N3E or N3B?

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process, Set for Volume Production in 2024

corp.mediatek.com

 

[deconstruct60]

Which node does Mediatek use for the SoC: N3E or N3B?

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process, Set for Volume Production in 2024

corp.mediatek.com

Since Mediatek did two iterations on N4 , pretty likely this is N3E. Just now taped out. ( that is no where near done either. ) . Mediatek spent the timeframe would/should have needed to do N3B development on N4 issues.
N3E is also cheaper and Mediatek doesn't have super deep pockets. ( Not broke but financially it would make lots more sense since they don't sell systems. They don't know exactly how many they need to make and N3B is too expensive to guess at inventory. )

P.S. ooops ... 3 interations on N4 . Looks like 9300 is on N4P.

https://wccftech.com/mediatek-dimensity-9300-supports-lpddr5t-ram/

this is suppose to be Q4 2023. So that "3nm" SoC is the "9400" there is very good chance Q3-Q4 2024. That late in 2024 just starting on N3B doesn't make much sense at all.

 

[Xiao_Xi]

If Apple uses N3B for the next generation SoC this year and other companies use N3E next year, could Apple have supply issues using N3E next year?

 

[deconstruct60]

If Apple uses N3B for the next generation SoC this year and other companies use N3E next year, could Apple have supply issues using N3E next year?

Apple A16 used N4P (N4?) while Mediatek was using N4 in 2022. ( MediaTek was first to ship a N4 class SoC offering. Not Apple). Not sure where huge overlap issue would be in 2024 if did the same thing on different node.

If Apple shifted the A17 off of N3B to N3E the main fab machines could/would just follow out of N3B. It would be a problem if TSMC assigned machines to N3B for work that was never going to come. But if most of leaves ... then can flip those over. The wafers spend less aggregate time inside the machine so net wafer production should actually go up on reassignment.

 

[theorist9]

N3E offers better clock than N3B but lower logic and SRAM density. When A17 rolls around for regular iPhone 16, SE, iPad, and Apple TV, I suspect Apple will constrain the die size meaning less SRAM.

I don't see the switch to N3E as a reason to reduce the number of transistors in the next generation of chips for these devices. Even if they keep the number of transistors the same (thus necessitating a larger die), it's still going to cost less than the same number of transistors on N3B, right? So given that they're already saving money, why would they go backwards on performance? I.e., when it comes to die cost, the bottom line isn't transistors/unit area, it's dollars/die.

Indeed, if the reports of the substantially lower cost of N3E over N3B are correct, N3E gives Apple the economic license to use more transistors (which would include more SRAM, if their designs call for it), not less.

 

[deconstruct60]

Which node does Mediatek use for the SoC: N3E or N3B?

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process

MediaTek Successfully Develops First Chip Using TSMC's 3nm Process, Set for Volume Production in 2024

corp.mediatek.com

and also.

N5 vs N3E chart here. "32% Power " " 18% performance"

TSMC Details 3nm Evolution: N3E On Schedule, N3P and N3X To Deliver 5% Performance Gains

www.anandtech.com

in press release "18% performance" "32% Power".

 

[deconstruct60]

I don't see the switch to N3E as a reason to reduce the number of transistors in the next generation of chips for these devices. Even if they keep the number of transistors the same (thus necessitating a larger die), it's still going to cost less than the same number of transistors on N3B, right?

the N3E wafer is presumably cheaper than N3E wafers , but the die is going to be bigger (~4% ) also ( so will get less dies per wafers as a result). cheaper wafers but use more is it still cheaper? ( depends on the discount gap between the two. )

There is a presumption by many that the N3B yields will still be 'horrible' at the 2 year mark after launch. That is little dubious. N3E will start high volume manufacturing at a higher yield , but will have less room to improve also. It likely will have a gap , but probably not huge.

The combo (incremental wafer reduction + incremental) yield probably means overshadow that 4%.

However, It is also going to cost money to re-spin A17 for N3E. ( useful if N3B is 'dead' when need more A16's in several years if go that route. If A17 dead ends before N3B dies , then can skip the re-spin costs. )

 

[MayaUser]

since the A17 will go for the efficiency more than power house that means we will have N3e or N3B for the M3 family as well ?

 

[theorist9]

since the A17 will go for the efficiency more than power house that means we will have N3e or N3B for the M3 family as well ?

1) Any performance/efficiency tradeoff they make for the A17 wouldn't necessarily apply to the M3. In fact, it wouldn't be surprising for it to be the opposite, where the benefits of the new process are mostly used to improve efficiency on the A17, but performance on the M3.

2) Unless there is something very specific they want to do that is only available on one process rather than the other (a hypothetical example: scale to significantly higher clocks on the M3 Studio and M3 Mac Pro), they will be able to make whatever efficiency/performance tradeoff they choose (within reason) with either process.

In summary, any choice they make to emphasize efficiency for the A17 should have no bearing on the process used for the M3.

 

[MayaUser]

so you dont think they will go for the M3 that is suppose to be for the ipads, and Macbook Air for efficiency ?
From some rumours i heard that M3 and M3 pro will be different from M3 Max that will be for more power than efficiency ?!
Maybe i read that wrong

 

[theorist9]

so you dont think they will go for the M3 that is suppose to be for the ipads, and Macbook Air for efficiency ?
From some rumours i heard that M3 and M3 pro will be different from M3 Max that will be for more power than efficiency ?!
Maybe i read that wrong

I can't speak to the iPads but, AFAIK, Apple has never released a new generation of Mac that has the same performance as the old one. They always go faster. And they need to, just to keep up, since both the OS's and applications continue to get increasingly complex (and thus increasingly computationally demanding).

Plus the Air's battery life is already spectacular. I think what's more important, and what they will do, is to try to maintain a performance improvement with each generation. If not, they give up their lead and even begin to get left behind.

Of course, this is just my own speculation.

I've read rumors that the M3's SC performance will be 30% higher than the M2's, which would be great to see.

 

[JPack]

As predicted, A17 Pro. Which means there will be mainstream A17.

N3B = Expensive, low-yielding, but higher performance A17 Pro.

N3E = Cheaper, higher yielding, lower performance A17 next year.

 

[leman]

As predicted, A17 Pro. Which means there will be mainstream A17.

N3B = Expensive, low-yielding, but higher performance A17 Pro.

N3E = Cheaper, higher yielding, lower performance A17 next year.

Yep, that’s a reasonable way to handle this.

 

[deconstruct60]

As predicted, A17 Pro. Which means there will be mainstream A17.

N3B = Expensive, low-yielding, but higher performance A17 Pro.

N3E = Cheaper, higher yielding, lower performance A17 next year.

If the plain A17 just tosses 1 GPU core , it won't be all that much 'lower performance'. 20% uplift in overall GPU and then drop 17% of the cores. They could still eek out a net uplift and the rest is still up while still clawing back some die space. ( just keep the core on the bigger die and do yield management will one turned off all time. )

The uplift on CPU isn't that high , so seems doubtful they'll backslide much on that. The NPUs ... backsliding on AI ... why?

Doesn't seem likely this is a 'Mn' vs 'Mn Pro' like gap.

 

[ghanwani]

We were excited to hear that TSMC started production of 3nm Apple Silicon last October. It has been half a year, where are those 3nm Mac?

They are everywhere. But they are so tiny, they cannot be seen by the naked eye.

 

[Gudi]

As predicted, A17 Pro. Which means there will be mainstream A17.

N3B = Expensive, low-yielding, but higher performance A17 Pro.

N3E = Cheaper, higher yielding, lower performance A17 next year.

So which features would you cut out to justify a new "non-Pro" name? Normally the exact same chip on a different process keeps its name.

 

[NT1440]

So which features would you cut out to justify a new "non-Pro" name? Normally the exact same chip on a different process keeps its name.

That USB controller is probably on the chopping block.

 

[JPack]

So which features would you cut out to justify a new "non-Pro" name? Normally the exact same chip on a different process keeps its name.

One of the biggest difference is 3nm offers almost no SRAM density improvement. I would expect smaller cache. GPU cuts for sure. Maybe also lower clock targets.

 

[NT1440]

One of the biggest difference is 3nm offers almost no SRAM density improvement. I would expect smaller cache. GPU cuts for sure. Maybe also lower clock targets.

I recall reading somewhere recently that SRAM is running into major hurdles with every shrink. Does that sound familiar to you at all?

Edit: Found it! https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/