Yep - as I said, I don't have a strong technical reason or issue at present, just fear of the past finding a way to repeat.
(and so far, I quite like my 'kind of thicker' M1 Max MBP14)
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Why Intel and AMD don't make chips like the M2 Max and M2 Ultra
- Thread starter sack_peak
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(and so far, I quite like my 'kind of thicker' M1 Max MBP14)Throttling is not a bad thing per her, it's one of the tools for the system designer to manage the system performance. The target power consumption for the AS MacBook Air is exactly the same as it was for the Intel MacBook Air, it's just that AS can reach much better performance at the same power consumption.
If the A17 Pro is any indication, the 3nm Mac chips will consume more power, not less. But they will also deliver better performance. Which would be perfectly fine anyway, as the Macs still have a lot of thermal headroom.
I want to imagine that thermal throttling is the system designer's last resort to keep the CPU/SoC running. Without this feature, the CPU/SoC would die from excess heat. So, it is OK if a CPU/SoC slows down from time to time, but not if it does so every day. If it slows down every day, it means that it's not up to the task in that environment.
Do we think M3 Pro/Max is going to have the same thermal boost "feature" that Intel and AMD have? As in having the CPU run higher (across all cores) than what it is rated for as long as there is thermal headroom.
That's really not how I see it. Thermal throttling is an absolutely viable method of power management. Not every system needs sustained performance. Many consumer systems operate in bursts. Maintaining the peak performance for only a few seconds can be a good strategy for some products.
I don't think this comparison is valid, as Apple's marketing is very different from Intel's. Apple does not have the concept of "rated" power level or frequencies. Intel's velocity boost instead is a marketing feature that allows them to advertise the CPUs as being faster than they actually are in practice.
If you are instead talking about the CPU behaviour in practice, that's how pretty much any Mac (Intel or Apple Silicon) has operated in the last decade or longer. The first limit is the frequency, the second is temperature. Apple never used TDP throttling, not even on Intel chips. It was always temperature.
I don't see the relationship of operating in burst with thermal throttling. For me, thermal throttling is a mechanism to cool a CPU/SoC by reducing the frequency and consequently performance when the temperature becomes unbearable.
Exactly. And most cooling systems provide thermal capacity that allows them to operate at higher power for a short time without any additional active cooling. It takes some time to reach a high enough temperature. For the MacBook Air this can be minutes. This is the time you can operate on higher frequency and it's often sufficient to get the job done. If the task takes longer, the system will reach the high temperature and subsequently throttle.
As I understand, thermal throttling is a feature of the CPU (processor). It's a safety mechanism which is absolutely necessary. But when it comes to the system as a whole (a computer) then there is more to it. The system (motherboard?) is monitoring CPU temperature. If it gets high, the computer may have the means to "help" the CPU by speeding up the fans etc. If that is the case, CPU may not need to throttle (for its temperature won't reach the dangerous levels). What the system can do depends on the computer design. If the computer does not have the fans, then I do not know what can be done but the thermal throttling. Apple in general loves to design the systems with passive cooling. If that is all there is and it is inadequate then there will be thermal throttling. Depending on one's use case, the "inadequate" part may vary. Those who rarely not run the computer hard may prefer lighter weight to better cooling.
I watched the 14700 and 14900 review on Gamers Nexus and 300 watts? Seriously? 6 Ghz? I guess that Intel isn't doing great with process node shrinks if this is the main direction that they're going towards.
Neither does 14xxx series, 6Ghz is strictly single-core. I wonder what frequencies they are hitting at these power consumption levels. If I remember correctly, the single-core 14900 power consumption was whopping 70 watts. That's 10-14x more power for 8% more performance compared to A17...
Of these new high-end Intel chips? 6-10x worse, depending how you measure (in multicore).
the 14th gen really has nothing to do with process node shrinks or not.
To a large extent, it is just a rebadge of the 13th gen. It has some more implementation fixes in it than anything to do with process node changes. It isn't like this is a 7++ ... it is basically just the same Intel 7 formula that 13th gen used but perhaps some very minor tweaks in process to improve yield (not resizing.)
There was a power regulation subsystem that they left turned off for gen 13 that is now fixed and turned on. It has more impact down the product matrix than at the top where they are 'juicing' the die so hard there is not much better regulation management can help. ( e.g. get i5's better at consuming max power, but not better i9's . Outside of posturing bragging rights forums that is probably more critical to holding market share . Lots of forum smoke and fire revolves about processors that AMD/Intel don't sell in relatively high amounts. )
Intel's major problem isn't process node shrinks. It is that for an extended period of time they had a shotgun approach to trying to charge into 8 different directions at the same time. Intel 4 was ready to go a while back, it was quirks in Meteor Lake design that took longer to iron out. Sapphire Rapids went through more than 10 steppings before it came out. Those aren't really fab problems.
The drama they have had on the dGPU side... those are fabbed on TSMC ... not really a fab problem there either. (design and drivers ).
Intel had the fab and CPU design way too intertwined and intradependent. Unwinding that is likely a major contributor reason for the need for a gap filler. The fab needs to work with more outside 'clients' and extrenal design tools. Likewise the CPU design team needs to use more tools that are portable to different fabs and not punt as many problems over the 'fence' to the fab to sort out for them.
Intel has fallen into the trap of trying to do everything for everybody. Intel 4 doesn't have to be good at everything. Laptop SoC packages are far more strategically critical to Intel mainstream packages than desktops. If they have to gap fill on desktops for a short while to get laptops 'straight' that is a very resaonable call. Likewise if have to wait on Intel 3 to move server forward... again a reasonable call. ( and perhaps not use Intel 3 on any mainstream SoC package at all. Intel could move destkop off onto TSMC N3 variant for an iteration before come back if that makes more sense timing wise. )
There haven't been many revolutions in hardware in a while now. Pretty much everything we've seen are evolutions and fine-tuning/specialisation. Hardware ray tracing is probably the only feature I'd describe as revolution but it hardly led to any revolution in software (yet). Machine learning is shaping up to be a revolution, but it's driven by evolution rather than revolution in hardware.
I was wondering if the faster ssd (NVMe) is creating a way way more efficient use of clockticks meaning the need for higher clockspeeds is simply not there anymore?
SSDs are important for what users perceive as responsive computers. Things like opening apps, loading files etc. But they don’t really contribute much to tasks that are traditionally CPU or GPU intensive.
To be fair, Meteor Lake is a really big step. First time they use EUV litho in production, first time they combine their new packaging technologies, mixing and matching Intel- and TSMC-manufactured tiles. Next year they will then make another generational step and move to GAA transistors and backside power delivery. They are iterating fast (they have to if they want to catch up to TSMC by '25), but aren't trying to do all at once (which was a major reason why they had so many problems with their 10nm process back in the day).
Yep, I think that's exactly what's happening. They may also not yet have enough EUV systems online to cover all segments with the newer processes. For their potential leading edge fab customers 18A will be the critical step.
That shouldn't be as much of an issue because Meteor Lake appears to be pretty close to just being a 'tick' shrink of about the same microarchitecture ( not a 'tock' or a heavy combo. ). Intel was suppose to get to EUV at end of 2021 so an extra 1-1.5 years.
I suspect the bigger hiccup that Meteor Lake could be these low-power E cores implemented on a completely different fab process and on another die. Multicore benchmarks that try to heavily lean on those to 'goose' the multicore scores might backfire in several contexts. Those are cores that apps shouldn't try to overtly use. [ allocation to those cores all driven by thread director and the host operating system only as appropriate. Very thread 'greedy' apps should just do ' minus 2' on the total core count on those packages. ]
It isn't the first time for multi-vendor packaging. There was Intel + AMD dGPU that they tried. However, for Forveros specifically though the INtel Max GPU (Ponte Vecchico)
" ...
| Die | Node | Contains | Area | Count | Total Area |
| Base | Intel 7 Foveros | Switch fabric, 144 MB of L2 cache, IO to HBM and peer GPUs | 640 mm2 | 1 | 640 mm2 |
| Compute | TSMC N5 | 8x Xe Cores | 40.31 mm2 | 8 | 322.47 mm2 |
| RAMBO | Intel 7 | Four 3.75 MB banks of extra L2 cache each | 14.17 mm2 | 4 | 60.66 mm2 |
| Xe Link | TSMC N7 | Cross-package links and switching logic | 74.12 mm2 | 1 | 74.12 mm2 |
..."
Intel’s Ponte Vecchio: Chiplets Gone Crazy
Intel is a newcomer to the world of discrete graphics cards, and the company’s Xe architecture is driving its effort to establish itself alongside AMD and Nvidia. We’ve seen Xe variants…
chipsandcheese.com
Meteor Lake is more an issue of whether Intel can do this at volume and ' affordability enough' pricing , rather than 'can they do it'. For Meteor Lake they need to produce 2-3 orders of more magnitude more packages. That is going to be a significant issue.
Intel already did PowerVia
Intel Details PowerVia Backside Power Delivery Technology
A key feature of Intel's 18A and 20A nodes revealed
More telling issue is whether anyone else would want to use Intel4+PV . Also what is real difference between this and Intel 3 (and if they got distracted with this away from what really should put in work on Intel 3 on).
The 20A coming in 2024 appears to be an excessive amount of 'tap dancing' on the notion of "appear".
It also smacks a bit of misdirection away from Intel 3 , which is another 'can they ramp into high volume production' open question while still 'juggling' a steady stream of Intel 4 production. ( there is only one new addition to an Intel Fab to do all the production for Intel 4 in Ireland. That's it. ) . The server products being on Intel 3 makes it strategically pretty critical for Intel also. Server is not the 'print money' profits division it used to be. It also is more critical than mainstream desktop.
" ... Perhaps the most interesting thing about the demo was what wasn’t said, however: the process node used for Lunar Lake’s compute (CPU) tile. In Intel’s earliest (and still most recent) public roadmap, Lunar Lake was listed to be built on the Intel 18A process. However, other disclosures from Intel today indicate that they’re only going to be starting risk production of 18A silicon in Q1’2024. Which means that for Lunar Lake to be working today, it can’t be on 18A. ..."
Pretty good chance that Lunar Lake is all "smaller die , all laptop" TSMC N3 (N3B by some recent reports. Intel sticking with what they initially mapped out to save costs and time. ). Not much of a huge gap between Arrow Lake and Lunar Lake except for some incremental improvements.
It won't be surprising if both 20A and 18A are both in 'at risk production' status basically all through 2024. Intel is going to point to "we are making batches" as 'appear in 2024'. How long those overlap in 'at risk' status will be an indicator of whether Intel is executing well or not.
Intel isn't iterating fast as much as chopping fab process jumps into smaller pieces. Intel 4 and 3 is what used to be just a single process node increase for them. ( Intel 4 does a subset. Intel 3 finishes the rest). 20A does a subset ... 18A finishes the rest. That way they 'double' their marketing roll outs .
I expect 18A is going to be relatively more expensive than any other option. Intel's 3D packaging is going to be critical because fab customers are probably going to want to put a relatively very small 18A die together with something else that is made on more affordable fab process that makes more sense. I think the high price is going to solve the potential 'high volume' problem there. Customers just won't buy very high wafer volume due to the cost.
Intel moving to pull 18A in front of reasonable availability of the ASML next gen EUV machines is going to put them into a similar 'boat' that TSMC got into with N3B . More multipatterning because at the tipping point the EUV fab machine generation can handle. All of that doesn't lead to 'affordable'.
It's still the first time they use EUV in production.
Yes, but that was before Gelsinger shook everything up.
Indeed. But production is already underway in their Ireland fab, so we'll soon see.
Not in production. It will come with 20A next year.
Not sure what "distraction" you mean. Intel 3 is an iteration of Intel 4 with denser libraries, and will be used for the 2024 server SKUs.
Huh? Intel 3 is used simply because Sierra Forrest and Granite Rapids will begin volume production before 20A.
Arrow Lake is an iteration of Meteor Lake. Lunar Lake has a new microarchitecture that's specifically optimized for power efficiency. It's essentially Intel's answer to Apple's M series.
I think their current pace is actually astounding. And making faster but smaller jumps seems like a good idea. The 10nm debacle happened in large part because they bit off more than they could chew.
Could be. But I bet they are willing to eat a temporarily reduced profit margin if they can attract a "whale" customer for their fab business, and that all pivots on 18A.
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Not according to current reports
“ …
unveiled the names of core designs from past iterations, like Meteor Lake’s “Redwood Cove”. Intel has now officially confirmed that the Lunar Lake chips will be powered by Lion Cove and Skymont. The former, labeled as ‘Cove,’ is anticipated to serve as the architecture for the large Performance cores, while ‘Mont’ is expected to drive the next-generation Efficient cores.
…”
Intel confirms Lunar Lake will feature "Lion Cove" P-Core and "Skymont" E-Core architectures - VideoCardz.com
Intel has confirmed the microarchitectures for its next-gen CPU series The company names the core architectures for its 2024/2025 low-power mobile series. Intel has recently provided several updates regarding its Lunar Lake CPU series. Among these, the most significant is the beginning of work...
Both Arrow Lske and Lunar Lake are using Lion Cove. Same CPU arch. The GPU arch is changing but that GPU is not solely targeted at low power . ( may be launching iGPU tile before the dGPU package goes out the door )
At a previous point in time, some rumors gave Lunar Lake a “Lion Cove + “ update from Arrow Lake. Recent reports suggest that got canned . Even earlier rumors had “Lunar Lake “ playing the same role that Panther or Nova Lake will now play much later.
Lunar Lake isn’t going to be answer to the M-series at all . It may be answer to M1 or M2 but not the whole series. LL is now rumored to top out at 8 cores . It will only match up to a subset of the series. It is the very high percentage of what Apple ships/sells , but it isn’t the whole series .
there will likely be a desktop Arrow Lake repurposed to be a laptop “HX” which won’t really match up with Apple at all but make the folks who want mobile dGPU in their system much happier .
[ the uncore , memory subsystem , NPU/AI , SoC tile may be updated but basic Core micro architecture isn’t going anywhere on this name transition .]
astounding ?
Intel used tick-tick to manage complexity for years
Tick–tock model - Wikipedia
until they got way too arrogant and decided that all their money meant there were immune to too much complexity .
TSMC ( and Samsung to an extent ) have rolled out. N7 with N6 follow on and N5 with N4 follow on . Those weren’t astounding . What Intel is calling 4/3 is rolling out 2 years late from their roadmaps 3-4 years ago.
Intel has mainly just stopped shooting thrmselves in the foot. All during the 10nm romp thru a swamp they had EUV machines up in Oregon at the process R&D center chugging along.
intel does not need a singular whale client . They need multiple clients . Intel is already in reduced profit margin zone and haven’t even started risk production on 18A . The GPU and most of AI stuff is burning through lots of money . Some of their server business market share losses are likely pragmatically permanent ( between better AMD and Arm server offerings ) . The losses in desktop are heading in the same direction .
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Getting back the thread's title question, see the story I posted here:
No. Gelsinger returned in Feb 2021. That is the beginning of 2021 , not the end. He oversaw the external renaming to better align with the industry usage of the 7/5/4/3 numbering , but the actual work was already in-flight before he arrived. Naming schemes are useful for external communication, but don't necessarily get you better actual product production.
Intel 4 versus 3
" ... Compared to Intel 4, Intel 3 promises an 18% higher performance per watt efficiency, denser high-performance library, reduced via resistance, and increased intrinsic drive current. ... "
Intel: 3nm Node Meets Yield and Performance Targets
Intel's 3nm Granite Rapids and Sierra Forest processors on track for 2024.
And Intel's description of PowerVia.
" ... To isolate the development of PowerVia, they took the well-proven transistors from the preceding Intel 4 process node and built a special in-between node with the power and interconnect design planned for Intel 20A. ..."
With PowerVia, Intel Achieves a Chipmaking Breakthrough
Intel’s Ben Sell explains how the company developed and proved the world's first backside power solution, taking a major step forward in chipmaking.
Hmm ... inbetween 4 and 2 ( 20A) is what?
If Intel 3 doesn't have the same 'power via' , it likely has major foundational groundwork support for the elements it needs to do the early tech validation work. It goes toward it not being "astounding". Yes it is technically challenging, but they suppose to be doing technically challenging work.
The disctraction is that Intel 3 appears to be a 'dead end' process node. Other than the server productions what is it being used for? Customers ????? Intel's misdirect on the newest 'shiny' 18A is in part to note that they haven't sign up any substantive work for the other fab processes. If they don't get a 18A customer it will likely turn into 16A or 14A ... it will rotate to the 'just around the next corner' process. That is a practice of distraction/misdirection.
If Intel 3 is competitively priced and decent why doesn't anyone want to use it. ( even Intel to a large extent. ).
Intel has a very limited number of EUV machines. The number of machines dedicated to Intel 3 just means that many less machines dedicated to 18A. If not selling Intel 3 because have little capacity to sell how are they going to have capcity to sell at 18A (with also fewer machines)? Too many nodes spread on top of too few machines isn't a 'bonus'.
Well over 50% of TSMC revenue is produced by their non bleeding edge fab processes. Has Intel rounded up any client to suck up some of the relatively vast 10nm/DUV fab infrastrucuture they have deployed? Is anyone even asking that question because Intel narrows the discussion down to the latest 'shiny' fab process? 'Distraction' is a quite apropos adjective to the tactic.