When the process size decreases, the transistor count typically does go up.
But let's suppose it didn't.
If it didn't how can the premise be actually true or even remotely close to accurate? Have a "smaller process size" but cannot make a primary basic element smaller/denser. Then why is being labeled as a "smaller process" if can't make denser things.
Some types of elements are starting to break off.
AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart...
www.techpowerup.com
If analog , memory ,
and logic all go flat then really don't have a "smaller process size" in the first place.
I don't believe that would cause a chip made with a smaller process to be cheaper. Yes, you need less area of silicon, but the decrease in cost due to a smaller die is probably small compared to all the costs that increase when you go to a smaller process, including higher purity requirements for the silicon, more stringent dust filtration requirements for the facility, more expensive photolithography machines to do finer etching, and the need to fabricate finer metal patterns for the BEOL phase (
https://en.wikipedia.org/wiki/Back_end_of_line).
If go to smaller die size then yields go up. An individual 70mm^2 dies aren't going to suffer the same defect rates as a 700mm^2 . The customers of a fab will sell the individual chips to end users , but they are largely paying to process a whole wafer. If there are zero or 500 defects on that wafer the cost is the same to fab customer.
If the customer only gets 20 dies they they can charge $60 for out of a $20K wafer than that is bad. ( 1.2 - 20 = -18.8K ). If they get 400 dies at $60 ( $24,000 - 20,000 = +4K ) then it isn't. If the wafer cost 15K then would make more money ( 9K ), but if have more stuff to sell then have more money to pay for stuff like defective dies and/or higher wafer costs.
The other factor you are ingoring is the possible other chips that are being gotten rid of. If go from
CPU package + DDR RAM + GPU package + VRAM down to CPU-GPU package + unified RAM then have chunked other packages because getting closing to being a more complete 'system on a chip'.
TSMC N3 is going to be better at some elements of a broad spectrum SoC than for others. Chasing much larger than normal caches with N3 , N2 , N1.8 , etc may not be the best use of the increasingly expensive fab process. Splitting some of that off into another chip/die may work better. Very large monolithic dies that cover broad elements types are going to get harder to do more affordably.
P.S. TSMC N3 is likely going to be better at making medium to large dies smaller than at making relatively small dies ( e.g., sub 100mm^2) dies even smaller. The FinFlex ( three different FinFet implementation options on single die will help target the density where it is most effective and leave off where it isn't. But probably limited in how much that helps to keep the overall different elements shrinking when do not have lots of them. )
