Agreed. Apple Silicone chips have proven to be ahead of all CPUs currently and the M1 clearly demonstrates how good they are.
Now, as per the cadence, I do believe we might see either a 14-18 month cadence depending on AMD/Intel offerings.
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Alleged Apple Chip Plans Suggest 'A16' Will Stick With 5nm, 'M2' to Make Jump to 3nm Instead
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Now, as per the cadence, I do believe we might see either a 14-18 month cadence depending on AMD/Intel offerings.
The problem with this idea is that we wouldn't see 3nm chips until 2024... I think we'll see 3nm M3 mac's next year.
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With the M2 being based on A15 and rumored to have nearly launched in Spring Event, I'd say that it's more likely than not that we're going to get yearly updates.
No one here has ever said that we're going to get a new Mac Pro or even a Mac Studio SoC every year.
We're all talking about the base M chips.
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All reports pointed to a Spring launch for the M2. A series in Fall. M series in Spring. Makes a lot of sense going forward.
No one knows for sure what the cadence is because we've only had a sample size of 2 and plenty of new chassis designs, lockdowns, supply chain issues, and inflation mixed in.
TSMC to start mass production of 3nm 'M2 Pro' later this year - 9to5Mac
Apple this week unveiled the new M2 chip, which is the first upgrade to the Apple Silicon chips created specifically...
9to5mac.com
Seems like everyone is of the opinion that TSMC’s 4nm process will be skipped by Apple.
If I'm not mistaken, 4nm is basically just a slightly updated version of TSMC's 5nm process. 3nm is their true "next generation" fab and will offer much bigger gains.
It'll be interesting to see what Apple does, but if 3nm is ready for mass production by the time the M3 is ready for the market, it might be worth it for Apple to wait.
According to Anandtech:
TSMC Roadmap Update: 3nm in Q1 2023, 3nm Enhanced in 2024, 2nm in 2025
Starting production has little to do with releasing a quantity of new SoCs. It can take more than a 3 months to get chips out of a fab after production starts. And Apple needs a large supply of SoCs to manufacture a new computer in production quantity. If TSMC starts 3nm production in the 4th quarter 2022, don't expect new Macs until around spring 2023 and maybe even later.Does it make sense for Apple to switch to TSMC 3nm for the M2 Pro? Would the M2 Pro be A16-based instead of A15?TSMC to start mass production of 3nm 'M2 Pro' later this year - 9to5Mac
Apple this week unveiled the new M2 chip, which is the first upgrade to the Apple Silicon chips created specifically...
Does it make sense for Apple to switch to TSMC 3nm for the M2 Pro? Would the M2 Pro be A16-based instead of A15?TSMC to start mass production of 3nm 'M2 Pro' later this year - 9to5Mac
Apple this week unveiled the new M2 chip, which is the first upgrade to the Apple Silicon chips created specifically...
If their 2017-2018 era plan was to release the M2 Pro in late Q4 2022 then yeah it makes some sense. It doesn't make sense if they planned to get it out toward the prior to October 2022.
The A10 and A10X were on two different processes. So Apple has done it before. It makes sense in part because the N5P that the M2 is on is 'old' ( compared to path Apple is normally on for last several years). TSMC first started shipping at risk N5P back in Q4 2020. That is coming up on two years ago once get to Q4 2022. So in Q4 2022 would it have made sense to make plans to put a you leading pro chip on N5P ? No. N4 , N4P , or something better would make more sense.
If Apple is looking to do a two die Max combo package for a "M2 Ultra" then they have a problem. The TSMC InFO-LSI technology they are using is limited to 1x reticle limit. They are only marginally under that now. If use N5P or N4 to make a bigger Max die then could blow past that limit and wouldn't have a "Ultra" option to ship. M2 Pro is just a "chopped down design" from the M2 Max baseline work... then if Max is going to N3 then the Pro would also as fall out (since it isn't a "main driver" design. It is just a derivative design. )
So the bigger dies in the line up do have a greater need for a shrink to keep their size the same even after sprinkles lots more stuff inside of each core and adds substantive bigger cache all around in various formats. The Max however is more sensitive than the Pro size die.
While jumping to N3 might have looked like a reasonably good plan back in 2018-2019 , it is a not so great plan now in 2022 with the shift of N3 start deeper into the 2H 2022. TSMC is going to start making high volume N3 stuff in 2022, but probably not going to get volume finished product packaged and ready to be soldered into systems in 2022.
Is that end of world for Apple? No. They'll have to tap dance around why they didn't finish in 2022 , but worldwide pandemic is a reasonable justification for a contributing cause. If they are 1 Quarter off it isn't a big deal.
P.S. As to whether A16 based ... well that would hinge on what A16 was on. If A16 is just mild (N4/N4P) shrink of A15 then M2 Pro would just be just a bigger shrink of largely the same stuff. ( perhaps squeeze in some cache expansion). Just using N3 to shrink more than N4/N4P would.
Or it could be a early preview of the A17 cores. [ 'plain' M2/A15 was pretty lightweight update so could get the A17 cores mapped out earlier and start to deploy with the M2 shrink. ]
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TSMC has commented on a finance analyst call that they expected to recognize some of the high volume manufacturing N3 revenue in Q1 2023. So Spring 2023 ( Late march) might be a stretch. Customers are likely getting them toward the early-middle part of Q1 if the money is significantly flowing in by the end of Q1 .
But yes they do not have all the bugs worked out so could slide into April. I would expect Apple though to just get going though before December. Leading with the most expensive low volume package they were going to do on N3 so the margins could temporarily soak up the "just before HVM" lower yields.
Kuo's stated reasoning here is a bunch of hooey.
"... A15 is made by TSMC N5P. Because N4 has no advantages vs. N5P, it's reasonable for A16 to stick with the N5P, implying that improvements in performance and power-saving from A16 should be limited. ..."
The A15 had to go into production in April-June 2021. N5P was in high volume manufacturing then. N4 was NOT !
N4 didn't go HVM until this year. So N4 had no advantage primarily because it was not an option for the iPhone 13.
Apple didn't ship it last year because there was no improvement. Apple skipped it because it wasn't ready.
N4 advange over N5P is that it is about 6% smaller. The A14 -> A15 grew about 23% ( about 88 mm2 to 108 mm2 ) . Is 6% going to claw back that whole 23% expansion? No. Is it better than nothing? Yes. If Apple is going to tinker with the A15 for the A16 and add 5% more to the A15 design then N4 would allow Apple to 'tread water' and stick to the 108 mm2 size they got instead of going even bigger ( heading for 113mm2 zone). The wafer savings when cranking out 50-100 million dies when can save 5% is real money. (even more so when there is constrained wafer supply ) .
Apple has margins so yet another bump to the die size for a second round of limited performance bump won't sink the company. But Apple is a "save a buck" company. So it won't be surprising to use N4. It could be that the silicon team is just stretched too thin (doing N3 and AR/VR socs , doing a watch update (which is still stuck on N7, getting a modem ready, etc. etc. ) and they just take the small hit because it is a small design tweak they don't have time for.
I don't find it likey that Apple will use M2 Pro/Max as lead products for brand new process. A17 is more likely a candidate for lead product for 3nm.
Apple still hasn't finished off the Mac Pro. They are more deeply in need of a "Mac Pro" SoC that would be a good pair with the "Ultra" size SoC for some "half sized" Mac Pro system. The M2 Max would be fall out from that if there was a high degrees of design overlap between it and the duo / quad tiles that Apple was using for the Mac Pro.
This "M2 Pro on N3" leak also mentions something about "Mac server" (which likely isn't a server but the Mac in a rackable box. )
The M2 N3 series could be designed around the same time as the A17. One is not leading the other. It is impractical to ship them all at the same time. AMD/Nvidia/Intel/Qualcomm ... folks with broad chip package line ups... do not ship the entirety of a single generation at one time.
They might. The M2 is bigger already and heat can become an issue if the dies increase respectively in the M2 Pro/Max chips. They might not go 3nm, but perhaps 4nm. Although to be fair, there are reports of the 4nm process not providing any substantial benefits over 5nm Gen2.
It is probably a complete farce that Apple is controlling the delay here. They probably had a plan back in 2017-2019 and that plan has had a number of external factors imposed on that that all of Apple's money can't buy their way out of.
If years ago they chose to use N3 then sliding into 2023 is not Apple's call.
N5P won't get them much in power saving if use the clock bumps to get performance boost on a substantively bigger die (more stuff consuming power).
Apple herding Mac updates into the Fall really don't make much sense. Especially when on the same process node that the A-series is ramping on at roughly the same time.
The M1 Pro/Max isn't that old that it desperately needs a new SoC this Fall. A 1-2 Quarter shift out of the early Fall would actually probably help.
The 'plain' M SoC would be quite stale by Fall 2022 so it needed an update in 2022. ( Spring would have worked well).
The "Mac Pro class" SoC is only "not stale" because they haven't even done one yet. It is at this point late. That's what the Fall 2022 target should have been. The SoC they don't even have a "version 1" of .
Spring '23 would be the same 1 years + (3 or 6 months) that was probably the window the plain M was going with ( Fall '20 -> Spring '22 ).
There is about zero good sense to putting the M-series SoCs on a 12 month cadence. Even less so back herding them into one specific Quarter ( or worse month) every year. That is horrible plan when fab updates are no where near strictly yearly cycles.
Nothing major over N5P but plain N5 , yes it does. Even TSMC said so.
".. The N4 enhancement to the 5nm family further improves performance, power efficiency and transistor density along with the reduction of mask layers and close compatibility in design rules with N5. .."
https://pr.tsmc.com/english/news/2831
It is a more affordable to make process (easier to manufacture ( faster paths though the fab process ) and it is smaller (less wafers consumed) ) , but not really a tool for engaging in tech porn benchmark score wars. The latter is the criteria that most forums participants are trying to throw it out the window on ( it won't lead to noticible score improvements. ). If only interested in the 'hot rodding' aspects, then N5P and N4 are about the same.
Nvidia is rolling out the 4000 series GPU on this later in 2022 (maybe early 2023 if hiccups creep in. but suppose to be 2022 ). Their data center CPU package is rolling out on N4N (probably a tweaked N4P. ) . Especially for bigger dies it is more helpful.
I laughed way too hard. Good one good sir. Well, if the 4nm brings improvements, then I'd say it's a safe bet Apple might use it the M2 Pro/Max.
We know (or can reasonably expect) that Apple will release N3-based 3 nm process Macs in 2023.
First, regardless of when in 2023 they come out, it wouldn't make sense for Apple to call those M2's, since they will use a significantly more advanced process than does what they've already called M2 (the N5P-based 5 nm process used in the M2 Air). Thus the N3-based Macs will be M3's.
Second, if Apple doesn't think they'll be able to release these M3's until fall 2023, it might make sense for them to do an M2 refresh of the Pro/Max/Ultra in fall 2022 (i.e., using Pro/Max/Ultra versions of the Air's M2). OTOH, if they're planing a spring 2023 release, they might skip M2 altogether for those higher-end Macs.
First, regardless of when in 2023 they come out, it wouldn't make sense for Apple to call those M2's, since they will use a significantly more advanced process than does what they've already called M2 (the N5P-based 5 nm process used in the M2 Air). Thus the N3-based Macs will be M3's.
Second, if Apple doesn't think they'll be able to release these M3's until fall 2023, it might make sense for them to do an M2 refresh of the Pro/Max/Ultra in fall 2022 (i.e., using Pro/Max/Ultra versions of the Air's M2). OTOH, if they're planing a spring 2023 release, they might skip M2 altogether for those higher-end Macs.
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I just want to point out that those decisions have already been made. Apple isn’t going to decide next winter or spring 2023 whether or not they should spin up an M2 Pro.
That type of decision has been made already. Development of new CPUs happens years in advance with engineering samples and what not.
Likely Apple is already running trials of M3 devices with either 4nm or 3nm. FYI, just because 3nm isn't released, doesn't mean it isn't undergoing validation. Usually, new process nodes are released for customers when it meets certain yield requirements.
You two seem to have misunderstood my post, taking it to mean I was implying that the decisions haven't already been made. I wasn't. I was simply saying:
1) That the 3 nm N3-based Macs will very likely be released in 2023 (barring the usual global pandemic/supply chain caveats), and when they are, they will be called M3, not M2.
2) If the M3 Pro/Max/Ultra are released in late 2023, Apple could do a late 2022 M2 update to these models; OTOH, if Apple releases the M3 Pro/Max/Ultra in early 2023, they'll probably skip M2 altogether for these models.
Translation to make #2 clearer for you: If Apple's scheduled release date for the M3 Pro/Max/Ultra is late 2023, there may also be an M2 refresh for these models scheduled for late 2022. OTOH, if Apple's scheduled release date for the M3 Pro/Max/Ultra is early 2023, they'll probably skip M2 altogether for these models.
Depends upon what the "1" , "2" , "3" means in the M1 , M2 , M3 name.
If it is 1st generation architecture, 2nd generation architecture , etc. Then if Apple primarily just shrinks the N5P core designs onto N3 then it technically could still be M2. The fab process and the general architecture don't have to be coupled.
Intel used to run Tick / Tock model.
" .. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). .. "
https://en.wikipedia.org/wiki/Tick–tock_model
It is a risk management strategy where only change one major attribute at a time so that have more ability to work around problems (i.e., more time to 'focus' a manageable set of issues. ) . Yes, Intel marketing slapped different names on those phases. But if are going to overlap in less than a year time ... you don't really have to. Actually, probably better not to.
Apple already did this once.
P and E cores Hurricane and Zephyr on 16nm on a large very bloated for an A-series die 125mm^2
Apple A10 - Wikipedia
[ For perspective the M1 is 119mm^2 . The average iPad Pro die over last several years was around 120-125mm^2 ]
P and E cores also Hurricane and Zephyr on 10nm on 96mm^2
Apple A10X - Wikipedia
[ a bit under usual iPad Pro die A9X 145mm^2 , A12X 127mm^2 ]
The A10X was the first major die design rolled out on 10nm. Turns out smaller than the A10 .
So suggestive that the number is mainly being used to talk about microarchitectural generation; not fab process.
But it is N3 , Apple can add "more cores" , more , more , more. That has an underlying presumption that N3 is easy to work with. That may not be the case. Given that TSMC is shifting to be back half of their 2H '22 time window is suggestive it is not super smooth sailing. And that might have had early indicators years ago ( if looks tough give ourselves an extra ,extra wide time window to hit). If getting onto the process is expected to be a bumpy ride than Intel's old tick-tock model is a pretty sensible move. Don't do major changes to the arch when move to new process. It is way less risky than messing with multiple dimensions at the same time.
TSMC has already mentioned that they are trying to pull forward a N3E process that is "enhanced" (which may just really be "easier to work with and get decent throughput through the fab " . ) Going to be a fair number of major players that are going to skip plain N3. ( AMD , Nvidia are just landing on N5 and N4... they could skip the initial N3 later just like Nvidia (and Qualcomm) are skipping N5 ).
Apple could add something like AV1. Limited scope , fixed function logic have been working on but never had enough "extra space" could be weaved in. ( Intel's ticks usually were never completely empty of any improvement. ). The major function blocks are just tweaked to be smaller. And they would have lots more leeway to crank boost clocks for single threaded drag racing "fun". If the Max size shrinks it would be easier (probably incrementally less expensive) to do two die Ultra packages. (could even just get rid of the chiplet path and just do monolithic "Ultra". If N3 is finicky then perhaps not. ) . Certainly, the quad die solution gets substantially more tractable if primarily focus on shrinking the Max class size dies.
They likely would not end up with a Intel/AMD desktop CPU package killer solutions at the higher end. However, they would be very competitive for lots of workloads. Wouldn't have a 4090 or 7900 killer GPU either, but competitive over a wide range.
Make it work. Then make it fast. With N3E, they could grow the Pro/Max/Ultra back up the current sizes. A "tock" phase.
After N3 (and its suffix variants ) comes Gate-all-around which likely will be another shift where could probably substantially lower risk by getting it right before going "buck wild" on microarch changes. Because shifting the arch those could be tagged M3. (and start trickling some of those out in 2024. Also not waiting around for N2. )
If A14 , A15 , and A16 are all on ever bigger N5 family dies that too could be due for a "tick" shrink with A17. Those are bloating way out the normal range like the A10 did. Also about the time where a new relatively very large modem subsystem is possibly either being weaved onto die or into the same package. Verson 1.0 of the modem probably makes sense to keep discrete though. At least a chunk of it.
Except the N3-based chips, in addition to being built on a different process from the N5P used for the M2 Air, are also going to have a different microarchitecture. I.e., both "tick" and "tock".Depends upon what the "1" , "2" , "3" means in the M1 , M2 , M3 name.
If it is 1st generation architecture, 2nd generation architecture , etc. Then if Apple primarily just shrinks the N5P core designs onto N3 then it technically could still be M2. The fab process and the general architecture don't have to be coupled.
Intel used to run Tick / Tock model.
" .. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). .. "
https://en.wikipedia.org/wiki/Tick–tock_model
It is a risk management strategy where only change one major attribute at a time so that have more ability to work around problems (i.e., more time to 'focus' a manageable set of issues. ) . Yes, Intel marketing slapped different names on those phases. But if are going to overlap in less than a year time ... you don't really have to. Actually, probably better not to.
Apple already did this once.
P and E cores Hurricane and Zephyr on 16nm on a large very bloated for an A-series die 125mm^2
Apple A10 - Wikipedia
en.wikipedia.org
[ For perspective the M1 is 119mm^2 . The average iPad Pro die over last several years was around 120-125mm^2 ]
P and E cores also Hurricane and Zephyr on 10nm on 96mm^2
Apple A10X - Wikipedia
en.wikipedia.org
[ a bit under usual iPad Pro die A9X 145mm^2 , A12X 127mm^2 ]
The A10X was the first major die design rolled out on 10nm. Turns out smaller than the A10 .
So suggestive that the number is mainly being used to talk about microarchitectural generation; not fab process.
But it is N3 , Apple can add "more cores" , more , more , more. That has an underlying presumption that N3 is easy to work with. That may not be the case. Given that TSMC is shifting to be back half of their 2H '22 time window is suggestive it is not super smooth sailing. And that might have had early indicators years ago ( if looks tough give ourselves an extra ,extra wide time window to hit). If getting onto the process is expected to be a bumpy ride than Intel's old tick-tock model is a pretty sensible move. Don't do major changes to the arch when move to new process. It is way less risky than messing with multiple dimensions at the same time.
TSMC has already mentioned that they are trying to pull forward a N3E process that is "enhanced" (which may just really be "easier to work with and get decent throughput through the fab " . ) Going to be a fair number of major players that are going to skip plain N3. ( AMD , Nvidia are just landing on N5 and N4... they could skip the initial N3 later just like Nvidia (and Qualcomm) are skipping N5 ).
Apple could add something like AV1. Limited scope , fixed function logic have been working on but never had enough "extra space" could be weaved in. ( Intel's ticks usually were never completely empty of any improvement. ). The major function blocks are just tweaked to be smaller. And they would have lots more leeway to crank boost clocks for single threaded drag racing "fun". If the Max size shrinks it would be easier (probably incrementally less expensive) to do two die Ultra packages. (could even just get rid of the chiplet path and just do monolithic "Ultra". If N3 is finicky then perhaps not. ) . Certainly, the quad die solution gets substantially more tractable if primarily focus on shrinking the Max class size dies.
They likely would not end up with a Intel/AMD desktop CPU package killer solutions at the higher end. However, they would be very competitive for lots of workloads. Wouldn't have a 4090 or 7900 killer GPU either, but competitive over a wide range.
Make it work. Then make it fast. With N3E, they could grow the Pro/Max/Ultra back up the current sizes. A "tock" phase.
After N3 (and its suffix variants ) comes Gate-all-around which likely will be another shift where could probably substantially lower risk by getting it right before going "buck wild" on microarch changes. Because shifting the arch those could be tagged M3. (and start trickling some of those out in 2024. Also not waiting around for N2. )
If A14 , A15 , and A16 are all on ever bigger N5 family dies that too could be due for a "tick" shrink with A17. Those are bloating way out the normal range like the A10 did. Also about the time where a new relatively very large modem subsystem is possibly either being weaved onto die or into the same package. Verson 1.0 of the modem probably makes sense to keep discrete though. At least a chunk of it.
The M1 chip was based on A14, and the M2 chip in the Air appears to be based on the A15. The N3 process chips released in 2023 aren't going to be A15-based.
So, again, it won't make sense to call them M2.
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