Except the N3-based chips, in addition to being built on a different process from the N4P used for the M2 Air, are also going to have a different microarchitecture. I.e., both "tick" and "tock".
First, the M2 isn't likely on N4P. If they are based on the A15 then it is N5P.
An absolute hard technological requirement coming from where?
They is no "Need to". There are some marketing "would be nice to" , but need? No.
The recent rumours are that the "M2 Pro and Max" are 12 cores ( which could easily just be 8+4 ) and < 40 GPU cores ( so could use the same 10 core GPU building block that the M2 has). Just shrink that.
It would be a substantially smaller die for both variants ----> can make more chips from substantially fewer wafers.
[ Apple has to use more wafers ? If N3 is taking several weeks longer to come out of the fab pipeline process, then that can be offset by getting more dies from wafers that will appear at end of the pipeline at a slower pace. So if get 80 instead of 100 wafers out the pipeline for a fixed amount of time but get the same number of usable dies then why not? It is the number of dies, not wafers, that go into products. And if the M2 systems were projected to sell even more units than the M1 generation then ... again need even more workable dies. So making more per wafer makes sense. ]
The performance gap from the M1 versions can be the 2E cores , 16-> 20 GPU / 32 -> 38 GPU core count increases, the NPU boost (that the baseline M2 has) , and better uncore ( maybe pick up DisplayPort 2.0 which wouldn't necessarily trigger a "micro arch generation shift" bump to move the generation number. The Pro/Max had ProRes and the plain M1 didn't. That wasn't a generation number shift. Neither would be adding AV1 to Pro/Max at least decode. )., N3 would give them more wiggle room on some single threaded drag racing clock bumps. All of those would be enough to do "oh look" way faster than Mac Intel models (even much of the entry Mac Pro 2019 on some tasks ). And incrementally better enough on the M1 variants.
Shrinking the Max is critical if they want to do a Ultra package inside of 1x reticle. So "just shrink" means actually can do the product versus not. So "just smaller" is a clear 'win' there. Being able to even make the product is critical step. ( if don't go N3 for the M2 Max then decent chance there is no Ultra directly derived from the standard Max die. ) Using N5P for A15 and M2 would slightly "suck" as get a more expensive die out it. As the dies get bigger that N5P process factor sucks more and more. That the 400mm^2 20% bloat is another 80mm^2 . That is about the size of an average A-series chip implementation. It can be real money down the drain in the aggregate , if going to sell millions of these. Let alone be blocked from using the necessary package technology.
On N3, will the floorplan need to get rejiggered ? Probably. Will they have to use some different implementation techniques in some places ? Probably. Does the instruction set semantics have to change because using N3 ? No; absolutely not. The software/firmware stack on top doesn't "have to" see any difference what so ever. That is whole reason why have an abstraction barrier; so it doesn't have to. If the software stack sees the same thing then it is the same generation.
The M1 chip was based on A14, and the M2 chip in the Air appears to be based on the A15. The N3 process chips released in 2023 aren't going to be A15-based.
An A15 microarchitecture on N5P or on N3 would still be an A15. It would be addition work than the normal path evolution (N5 and N3 need different design rules but porting to N3 is not impossible. )., It is lots less work than tweaking the microarchitecture
and the process node at the same time.
AMD has a Ryzen 6000 APU that is on TSMC N6. The Zen 3 come out on N7. There are still a Zen 3 cores on the Ryzen 6000 . Can try to get bogged down in " But AMD changed from Ryzen 5000 to 6000 so the number had to change" , skips over the fact that AMD did not change the number on "Zen" . Both have Zen 3.
AMD is going to roll out a "AMD Mendicino" entry level APU with Zen 2 and RNDA 2 GPU cores on TSMC 6 . Yes, going from N7 -> N6 is an easier design rule port .
Apple can bubble up which ever marketing number they want to the package. Apple also doesn't have 6-8 packages per subset of the product line. (not much empty space left in the 5000 numbering scheme so jump to 6000 scheme to roll out another 6-89 packages). The 8CPU-8GPU is a M2 and the 8CPU-10GPU is a M2 . Quite illustrative that Apple is not doing so same package number scheme that AMD/Intel use. In part, because they have about an order of magnitude fewer packages types to sell. Not trying to sell everything to everybody. So do not need that many numbers churned each generation. If the microarchitecture is a '2' then put a '2' on the package ID.
. Whatever we try to infer will be subject to (hopefully rare) affects of the pandemic.
