### Start: AGDC[9] 0x10000240e ###############################################
IOService:/AppleACPIPlatformExpert/PCI0@0/AppleACPIPCI/PEG2@1,2/IOPP/UPSB@0/IOPP/DSB1@1/IOPP/UPS0@0/IOPP/pci-bridge@1/IOPP/pci-bridge@0/IOPP/pci-bridge@0/IOPP/display@0/AMDRadeonX6000_AmdAgdcServices/AppleGraphicsDevicePolicy/AGDPClientControl
Vendor: AMD [00001002]: DiscreteGPU [2 30000] (0)
FBs: 4, Ports: 0x1e mst:0xe ddc:0x1e aux:0xe, Streams: dp:6 dvi:4 mst:6 max:6
Framebuffers:
* 0: Address: 2.0 Stream: Enabled Group: -1 Online Assoc'd MayGroup
1: Address: 0.0 Stream: Not Associated Group: -1 MayGroup
2: Address: 0.0 Stream: Not Associated Group: -1 MayGroup
3: Address: 0.0 Stream: Not Associated Group: -1 MayGroup
Port Capabilities:
1: AUX, DDC, MST
* 2: AUX, DDC, MST
3: AUX, DDC, MST
4: DDC
Connections:
1:
* 2: [DP 1.4 4 x HBR2] Status: [4 x HBR2 7777] caps [features 0x101141b, p_encoding 0xd] Sink OUI:000-016-250 D1baba [068-049-098-097-098-097] HW Version: 17 FW Version: 6.56
3:
4:
## Register Dump Port 2 - Start ##
000000: 0x14 0x14 0xc4 0x83 0x01 0x00 0x01 0xc0 0x02 0x01 0x04 0x01 0x20 0x00 0x84 0x00
Reg: 000000: 14 : DPCD_REV: 1.4
Reg: 000001: 14 : MAX_LINK_RATE: HBR2
Reg: 000002: c4 : MAX_LANE_COUNT: 4, TPS3_SUPPORTED: 1, ENHANCED_FRAME_CAP: 1
Reg: 000003: 83 : MAX_DOWNSPREAD: 0.5% down, NO_AUX_HANDSHAKE_LINK_TRAINING: 0
Reg: 000004: 01 : NORP: 1
Reg: 000005: 00 : DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT: 0, DWN_STRM_PORT_TYPE: [0] DisplayPort, FORMAT_CONVERSION: 0, DETAILED_CAP_INFO_AVAILABLE: 0
Reg: 000006: 01 : MAIN_LINK_CHANNEL_CODING: ANSI 8B/10B
Reg: 000007: c0 : DOWN_STREAM_PORT_COUNT: DWN_STRM_PORT_COUNT: 0, MSA_TIMING_PAR_IGNORED: 1, OUI: 1
Reg: 000008: 02 : RECEIVE_PORT0_CAP_0: LOCAL_EDID_PRESENT: 1, ASSOCIATED_TO_PRECEDING_PORT: 0
Reg: 000009: 01 : RECEIVE_PORT0_CAP_1: BUFFER_SIZE: 64
Reg: 00000a: 04 : RECEIVE_PORT1_CAP_0:
Reg: 00000b: 01 : RECEIVE_PORT1_CAP_1:
Reg: 00000c: 20 : I2C Speed: 1Mbps
Reg: 00000d: 00 : eDP_CONFIGURATION_CAP: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 0, FRAMING_CHANGE_CAPABLE: 0
Reg: 00000e: 84 : TRAINING_AUX_RD_INTERVAL: 0 RESERVED, EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: YES
Reg: 00000f: 00 : ADAPTER_CAP: FORCE_LOAD_SENSE_CAP: 0, ALTERNATE_I2C_PATTERN_CAP: 0
000020: 0x00 0x00 0x01
Reg: 000020: 00 : FAUX_CAP: FAUX_CAP: 0
Reg: 000021: 00 : MSTM_CAP: MST_CAP: 0
Reg: 000022: 01 : NUMBER_OF_AUDIO_ENDPOINTS: 1
000060: 0x01 0x21 0x00 0x0f 0x0b 0x04 0x00 0x00 0x00 0x01 0x0e 0x02 0x0c 0x00 0x00 0x00
Reg: 000060: 01 : DSC Support: 1
Reg: 000061: 21 : DSC Algorithm revision: 33
Reg: 000062: 00 : DSC RC Buffer Block size: 0
Reg: 000063: 0f : DSC RC Buffer size: 15
Reg: 000064: 0b : DSC slice Capabilities 1 : 11
Reg: 000065: 04 : DSC Line buffer bit depth: 4
Reg: 000066: 00 : DSC Block prediction support: 0
Reg: 000067: 00 : DSC Maximum bit per pixel: 0
Reg: 000068: 00 : DSC Maximum bit per pixel: 0
Reg: 000069: 01 : DSC Decoder color format capabilities: 1
Reg: 00006a: 0e : DSC decoder color depth capabilities: 14
Reg: 00006b: 02 : DSC Peak Throughput: 2
Reg: 00006c: 0c : DSC Maximum Slice width: 12
Reg: 00006d: 00 : DSC Slice capabilities 2: 0
Reg: 00006e: 00 : Reserved: 0
Reg: 00006f: 00 : DSC Bits per pixel increment: 0
000090: 0x0f
Reg: 000090: 0f : FEC Capability: 0xf
000080: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Reg: 000080: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000081: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000082: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000083: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000084: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000085: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000086: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000087: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000088: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 000089: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008a: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008b: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008c: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008d: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008e: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
Reg: 00008f: 00 : DETAILED_CAP_INFO_AVAILABLE: DWN_STRM_PORTX_CAP: [0] DisplayPort, DWN_STRM_PORTX_HPD: 0, NON_EDID_DWN_STRM_PORTX_ATTRIBUTE: 0
000100: 0x14 0x84
Reg: 000100: 14 : LINK_BW_SET: HBR2
Reg: 000101: 84 : LANE_COUNT_SET: LANE_COUNT_SET 4, ENHANCED_FRAME_EN: 1
000107: 0x10
Reg: 000107: 10 : DOWNSPREAD_CTRL: SPREAD_AMP: 1, MSA_TIMING_PAR_IGNORE_EN: 0
00010a: 0x00
Reg: 00010a: 00 : eDP_CONFIGURATION_CAP_SET: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 0, FRAMING_CHANGE_CAPABLE: 0
000111: 0x00
Reg: 000111: 00 : MSTM_CTRL: UPSTREAM_IS_SRC:0 UP_REQ_EN:0 MST_EN:0
000120: 0x00
Reg: 000120: 00 : FEC Configuration: 0x0
000160: 0x01
Reg: 000160: 01 : DSC Enable: 0x1
000200: 0x41 0x04 0x77 0x77 0x01 0x05 0x22 0x22
Reg: 000200: 41 : SINK_COUNT: SINK_COUNT 1, CP_READY: 1
Reg: 000202: 77 : LANE0: CR_DONE: 1, CHANNEL_EQ_DONE: 1, SYMBOL_LOCKED: 1
Reg: 000202: 77 : LANE1: CR_DONE: 1, CHANNEL_EQ_DONE: 1, SYMBOL_LOCKED: 1
Reg: 000203: 77 : LANE2: CR_DONE: 1, CHANNEL_EQ_DONE: 1, SYMBOL_LOCKED: 1
Reg: 000203: 77 : LANE3: CR_DONE: 1, CHANNEL_EQ_DONE: 1, SYMBOL_LOCKED: 1
Reg: 000205: 05 : SINK_STATUS: RECEIVE_PORT_0_STATUS: 1, RECEIVE_PORT_1_STATUS: 0
Reg: 000206: 22 : LANE0: VOLTAGE_SWING: 2, PRE-EMPHASIS: 0
Reg: 000206: 22 : LANE1: VOLTAGE_SWING: 2, PRE-EMPHASIS: 0
Reg: 000207: 22 : LANE2: VOLTAGE_SWING: 2, PRE-EMPHASIS: 0
Reg: 000207: 22 : LANE3: VOLTAGE_SWING: 2, PRE-EMPHASIS: 0
00020f: 0x00
Reg: 00020f: 00 : DSC Status: 0
000280: 0x00
Reg: 000280: 00 : FEC Status: 0
000427: 0x00
Reg: 000427: 00 : Secondary HPD is controlled by: [0] TCON Policy, Secondary HPD status: 0, Desired HPD state: 0, Reserved: 0
00042f: 0x01
Reg: 00042f: 01 : DISPLAY_ROTATION: 0x1
002200: 0x14 0x14 0xc4 0x83 0x01 0x00 0x01 0xc0 0x02 0x01 0x04 0x01 0x0f 0x00 0x84 0x00
Reg: 002200: 14 : DPCD_REV: 1.4
Reg: 002201: 14 : MAX_LINK_RATE: HBR2
Reg: 002202: c4 : MAX_LANE_COUNT: 4, TPS3_SUPPORTED: 1, ENHANCED_FRAME_CAP: 1
Reg: 002203: 83 : MAX_DOWNSPREAD: 0.5% down, NO_AUX_HANDSHAKE_LINK_TRAINING: 0
Reg: 002204: 01 : NORP: 1
Reg: 002205: 00 : DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT: 0, DWN_STRM_PORT_TYPE: [0] DisplayPort, FORMAT_CONVERSION: 0, DETAILED_CAP_INFO_AVAILABLE: 0
Reg: 002206: 01 : MAIN_LINK_CHANNEL_CODING_SET: ANSI 8B/10B
Reg: 002207: c0 : DOWN_STREAM_PORT_COUNT: DWN_STRM_PORT_COUNT: 0, MSA_TIMING_PAR_IGNORED: 1, OUI: 1
Reg: 002208: 02 : RECEIVE_PORT0_CAP_0: LOCAL_EDID_PRESENT: 1, ASSOCIATED_TO_PRECEDING_PORT: 0
Reg: 002209: 01 : RECEIVE_PORT0_CAP_1: BUFFER_SIZE: 64
Reg: 00220a: 04 : RECEIVE_PORT1_CAP_0:
Reg: 00220b: 01 : RECEIVE_PORT1_CAP_1:
Reg: 00220c: 0f : I2C Speed: 1Kbps 5Kbps 10Kbps 100Kbps
Reg: 00220d: 00 : eDP_CONFIGURATION_CAP_SET: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 0, FRAMING_CHANGE_CAPABLE: 0
Reg: 00220e: 84 : TRAINING_AUX_RD_INTERVAL: 0 RESERVED, EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: YES
Reg: 00220f: 00 : ADAPTER_CAP: FORCE_LOAD_SENSE_CAP: 0, ALTERNATE_I2C_PATTERN_CAP: 0
068028: 0x01
Reg: 068028: 01 : HDCP_CAPABLE: 1, REPEATER: 0
06921d: 0x02 0x00 0x02
Reg: 06921d: 02 : VERSION: 2
Reg: 06921f: 02 : HDCP_CAPABLE: 1, REPEATER: 0
069330: 0x00 0x00
Reg: 069330: 00 : HDCP_Depth: 0
Reg: 069331: 00 : HDCP_count: 0 HDCP2_0 Downstream: 0 HDCP1 Downstream: 0
069493: 0x00
Reg: 069493: 00 : Ready: 0 , H' Available: 0, Pairing_available: 0 , Reauth_req: 0, Link Integrity: 0
## Register Dump Port 2 - End ##
## EDID Dump Port 2 - Start ##
// EDID Dump: device, 640 bytes, OK
uint8_t EDID_APP_610_ae2d[] = {
/* 000: */ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
/* 008: */ 0x06, 0x10, 0x2d, 0xae, 0x01, 0x14, 0x06, 0x35,
/* 010: */ 0x01, 0x1d, 0x01, 0x04, 0xc5, 0x46, 0x27, 0x78,
/* 018: */ 0x00, 0x0f, 0x91, 0xae, 0x52, 0x43, 0xb0, 0x26,
/* 020: */ 0x0f, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
/* 028: */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
/* 030: */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x42, 0xce,
/* 038: */ 0x00, 0x50, 0xf0, 0x70, 0x55, 0x80, 0x08, 0x20,
/* 040: */ 0x78, 0x00, 0xbb, 0x89, 0x21, 0x00, 0x00, 0x1a,
/* 048: */ 0x42, 0xce, 0x00, 0x50, 0xf0, 0x70, 0x16, 0x82,
/* 050: */ 0x08, 0x20, 0x88, 0x00, 0xbb, 0x89, 0x21, 0x00,
/* 058: */ 0x00, 0x1a, 0xa0, 0x5c, 0x00, 0x50, 0xa0, 0xa0,
/* 060: */ 0x39, 0x50, 0x08, 0x20, 0xb8, 0x08, 0xbb, 0x89,
/* 068: */ 0x21, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0xfc,
/* 070: */ 0x00, 0x50, 0x72, 0x6f, 0x44, 0x69, 0x73, 0x70,
/* 078: */ 0x6c, 0x61, 0x79, 0x58, 0x44, 0x52, 0x04, 0xd0,
/* 080: */ 0x02, 0x03, 0x0f, 0x80, 0xe3, 0x05, 0x00, 0x00,
/* 088: */ 0xe6, 0x06, 0x01, 0x01, 0x6b, 0x6b, 0x02, 0x3c,
/* 090: */ 0xce, 0x00, 0x50, 0xf0, 0x70, 0x57, 0x80, 0x08,
/* 098: */ 0x20, 0x98, 0x00, 0xbb, 0x89, 0x21, 0x00, 0x00,
/* 0a0: */ 0x1a, 0x3d, 0xce, 0x00, 0x50, 0xf0, 0x70, 0x86,
/* 0a8: */ 0x82, 0x08, 0x20, 0x88, 0x0c, 0xbb, 0x89, 0x21,
/* 0b0: */ 0x00, 0x00, 0x1a, 0x41, 0xce, 0x00, 0x50, 0xf0,
/* 0b8: */ 0x70, 0x89, 0x82, 0x08, 0x20, 0xb8, 0x0c, 0xbb,
/* 0c0: */ 0x89, 0x21, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
/* 0c8: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0d0: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0d8: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0e0: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0e8: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0f0: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0f8: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbb,
/* 100: */ 0x70, 0x12, 0x79, 0x00, 0x00, 0x29, 0x00, 0x10,
/* 108: */ 0x83, 0x4d, 0xb4, 0x8b, 0xde, 0x35, 0x43, 0x41,
/* 110: */ 0x9e, 0xb6, 0x86, 0x97, 0xa0, 0x41, 0x1a, 0x9e,
/* 118: */ 0x01, 0x00, 0x0c, 0x52, 0x1b, 0x5e, 0x0f, 0x80,
/* 120: */ 0x17, 0x38, 0x0d, 0x10, 0x78, 0x4e, 0xbb, 0x7f,
/* 128: */ 0x81, 0x07, 0xfa, 0x10, 0x00, 0x04, 0x01, 0x00,
/* 130: */ 0x00, 0x7e, 0x00, 0x05, 0x3a, 0x02, 0x92, 0x81,
/* 138: */ 0x00, 0x03, 0x00, 0x28, 0xc4, 0x6c, 0x01, 0x04,
/* 140: */ 0xff, 0x13, 0x4f, 0x00, 0x07, 0x80, 0x1f, 0x00,
/* 148: */ 0x3f, 0x0b, 0x70, 0x00, 0x62, 0x00, 0x07, 0x00,
/* 150: */ 0x58, 0xf6, 0x01, 0x84, 0x7f, 0x17, 0x4f, 0x00,
/* 158: */ 0x07, 0x80, 0x1f, 0x00, 0x37, 0x0d, 0x83, 0x00,
/* 160: */ 0x75, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 168: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 170: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 178: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x90,
/* 180: */ 0x70, 0x12, 0x79, 0x00, 0x00, 0x03, 0x00, 0x64,
/* 188: */ 0xc4, 0x6c, 0x01, 0x04, 0xff, 0x13, 0x4f, 0x00,
/* 190: */ 0x07, 0x80, 0x1f, 0x00, 0x3f, 0x0b, 0x70, 0x00,
/* 198: */ 0x62, 0x00, 0x07, 0x00, 0xa5, 0x6c, 0x01, 0x04,
/* 1a0: */ 0xff, 0x13, 0x4f, 0x00, 0x07, 0x80, 0x1f, 0x00,
/* 1a8: */ 0x3f, 0x0b, 0x72, 0x00, 0x64, 0x00, 0x07, 0x00,
/* 1b0: */ 0xb5, 0x6c, 0x01, 0x04, 0xff, 0x13, 0x4f, 0x00,
/* 1b8: */ 0x07, 0x80, 0x1f, 0x00, 0x3f, 0x0b, 0xc6, 0x02,
/* 1c0: */ 0xb8, 0x02, 0x07, 0x00, 0xbe, 0x6c, 0x01, 0x04,
/* 1c8: */ 0xff, 0x13, 0x4f, 0x00, 0x07, 0x80, 0x1f, 0x00,
/* 1d0: */ 0x3f, 0x0b, 0x5c, 0x03, 0x4e, 0x03, 0x07, 0x00,
/* 1d8: */ 0xab, 0x6c, 0x01, 0x04, 0xff, 0x13, 0x4f, 0x00,
/* 1e0: */ 0x07, 0x80, 0x1f, 0x00, 0x3f, 0x0b, 0x5f, 0x03,
/* 1e8: */ 0x51, 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 1f0: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 1f8: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x90,
/* 200: */ 0x70, 0x12, 0x79, 0x00, 0x00, 0x03, 0x00, 0x64,
/* 208: */ 0x58, 0xf6, 0x01, 0x84, 0x7f, 0x17, 0x4f, 0x00,
/* 210: */ 0x07, 0x80, 0x1f, 0x00, 0x37, 0x0d, 0x83, 0x00,
/* 218: */ 0x75, 0x00, 0x07, 0x00, 0x45, 0xf6, 0x01, 0x04,
/* 220: */ 0x7f, 0x17, 0x4f, 0x00, 0x07, 0x80, 0x1f, 0x00,
/* 228: */ 0x37, 0x0d, 0x86, 0x00, 0x78, 0x00, 0x07, 0x00,
/* 230: */ 0x52, 0xf6, 0x01, 0x04, 0x7f, 0x17, 0x4f, 0x00,
/* 238: */ 0x07, 0x80, 0x1f, 0x00, 0x37, 0x0d, 0x42, 0x03,
/* 240: */ 0x34, 0x03, 0x07, 0x00, 0x58, 0xf6, 0x01, 0x04,
/* 248: */ 0x7f, 0x17, 0x4f, 0x00, 0x07, 0x80, 0x1f, 0x00,
/* 250: */ 0x37, 0x0d, 0xf2, 0x03, 0xe4, 0x03, 0x07, 0x00,
/* 258: */ 0x4c, 0xf6, 0x01, 0x04, 0x7f, 0x17, 0x4f, 0x00,
/* 260: */ 0x07, 0x80, 0x1f, 0x00, 0x37, 0x0d, 0xf6, 0x03,
/* 268: */ 0xe8, 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 270: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 278: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x90
};
## EDID Dump Port 2 - End ##
## Display Connection Stats Dump Port 2 - End ##
Display mfgName: APP, productID: 0xae2d
Time to EDID read: 1239
Time to link train: 2364638
Link training duration: 55766
Link training status: 1
Link training count: 2
HDCP status: 0
HDCP retry count: 1
EFI w/a data: 0x0
## Display Connection Stats Dump Port 2 - End ##
### End: AGDC[9] 0x10000240e (took 0.302 sec) ################################