CXL is a device connection and state synchronization protocol that uses PCIe to transmit data. It’s something entirely different. It’s a technology designed to facilitate cache-coherent communication in large systems that are comprised from different devices connected via PCI lanes. It has no value for Apple who rely on tight physical integration. CXL is not suitable for multi-chip connections and is not an alternative to UktraFusion.
Relatively little doubt that Apple looks down its nose at CXL . However the bit about useless for chip to chip interconnect … somebody forgot to forward that memo to Intel . Covered at Hot Chips 34 that the Meteor Lake iGPU is leveraging it .
“… Intel says the CPU and SoC tiles communicate with the IDI protocol, while the iGPU tile uses an iCXL protocol to talk to the SoC. The SoC and IO extender tile are connected via IOSF (Integrated On-chip system Fabric) and DisplayPort.
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But Meteor Lake’s iGPU swaps over to iCXL, an internal implementation of Compute Express Link (CXL) that doesn’t use a PHY. CXL is based off of PCI Express, and like PCI Express, is meant to connect a CPU to IO devices. Compared to PCIe, CXL 3.0 allows better hardware handling of cache coherency, adds latency-optimized message formats (flits), and can accept a wider variety of devices by implementing three sub-protocols – CXL.io, CXL.cache, and CXL.mem. … “
During a presentation at Hot Chips 34, Intel detailed how their upcoming Meteor Lake processors employ chiplets. Like AMD, Intel is seeking to get the modularity and lower costs associated with usi…
chipsandcheese.com
Intel isn’t trying to make the CPU cores share maximum amount of L3 with GPU cores ( article examines some hit rates ). They also aren’t trying to make CPU and GPU share exact same fab process node either.
As mentioned, CXL is mostly a protocol on top … so can put it on a custom something built for super short distances also . Probably uses more power than some other options
Apple runs a proprietary PCIe variance from the SSD controller to the ”SSD modules” .
Longer term UCIe would also be a candidate for Intel internally . But dGPU with CXL are coming in intermediate future. Intel doesn’t have to worry about interoperability inside of Gen 14 ( Meteor Lake ) so can get a version 0.5 rolling there of that kind of setup . If Intel completely collapses their dGPU efforts long term would likely see a switch to something else . ( in part this is Intel trying to cover multiple markets and directions at the same time. ) .
I would be very very surprised if Intel uses CXL to connect the individual dies in a Sapphire Lake package, unless they are ok with the intra-die connection being dead slow.
They don’t , but that isn’t the only multi tile SoC they are working on .
The primary point of Apple’s SoC is not to work with other peoples’ high bandwidth stuff . ( at least so far ) No 3rd party GPU drivers is the extra cherry on top .
The vendors adopting CXL actually have interoperability as a substantive priority . So Intel , AMD , Nvidia, etc put it in On these next iterations . Even more so for vendors looking to be OAM ( open accelerator modules ) system players.