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quarkysg

macrumors 65816
Oct 12, 2019
1,247
841
Yes, they do :) It's just the question where are they going with all that. Their desktop strategy in the last couple of years was... inconsistent at best. Will they leave those models as entry level pricey lifestyle products, will they try to improve the performance to match mid-level PCs, or will they continue treating them as an afterthought?
My thoughts would be that Apple will not want to go into current mid-level PCs territory, as that would mean cranking their SoC energy usage level up for not much benefit.

I think Apple are pretty much comfortable with their Mx Pro, Max and Ultra line-up for desktop for mid-high range desktops. Quite unlikely for Apple to come up with another range for desktops other than for the Mac Pro.
 

leman

macrumors Core
Oct 14, 2008
19,520
19,670
My thoughts would be that Apple will not want to go into current mid-level PCs territory, as that would mean cranking their SoC energy usage level up for not much benefit.

That’s possible, although I do hope that they will eventually crank up the power consumption. Apple definitely has a lot of headroom compared to the competitors and a faster base Mac Mini/iMac would have so much better value proposition. But then again, the bottleneck still seem to the the supply, so not much point in increasing demand.
 

leman

macrumors Core
Oct 14, 2008
19,520
19,670
Since RISC-V is developing instructions for interpreted and JIT compiled languages, I can imagine that ARM and x86 ISA have similar instructions.

Is ARM ISA better than x86 ISA for interpreted or compiled JIT languages?

From a cursory glance this seems to be about more efficient support for tagged pointers (packing additional metadata into the unused bits of a data pointer to save memory/improve performance). ARM has supported this for a while via its' top byte ignore feature (which Apple uses extensively). Intel and AMD offer similar features.
 
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mi7chy

macrumors G4
Oct 24, 2014
10,619
11,293
In an interview with Tom's Hardware, Mark Papermaster, AMD's CTO, explains that the future of AMD chips and look a lot like Apple's Mx: BIG.little hybrid architecture with AI accelerators.

Where does it say that in the article? Only thing mentioned is:

"The highlights of the interview include Papermaster’s new revelation that AMD will bring hybrid architectures to its lineup of consumer processors in the future, a first. These types of designs use larger cores designed for performance mixed in with smaller efficiency cores, much like Intel’s competing 13th-Gen chips."

Plus, Qualcomm had big.LITTLE with AI Engine in 2015 with Snapdragon 820.
 

Xiao_Xi

macrumors 68000
Oct 27, 2021
1,627
1,101
Where does it say that in the article?
Mark Papermaster: What you're going to see in PCs, as well as in the data center, is more bifurcation of tailored SKUs and processers coming out. Because it's really now where one size doesn't fit all; we're not even remotely close to that. You're going to have a set of applications that actually are just fine with today's core count configurations because certain software and applications are not rapidly changing. But what you're going to see is that you might need, in some cases, static CPU core counts, but additional acceleration.

So, if you look at what we've done in desktop for Ryzen, we've actually added a GPU with our CPU. And that's because it really creates a very dense and power-efficient offering, and if you don't need a high-performance GPU, you can save energy with that sort of tailored configuration. If you do need tailored, extensive acceleration, you can still bolt on a discrete GPU. And the other example in PCs is the Ryzen 7040; we've actually added AI acceleration right into the APU.

But what you'll also see is more variations of the cores themselves, you'll see high-performance cores mixed with power-efficient cores mixed with acceleration. So where, Paul, we're moving to now is not just variations in core density, but variations in the type of core, and how you configure the cores. It's not only how you've optimized for either performance or energy efficiency, but stacked cache for applications that can take advantage of it, and accelerators that you put around it.
 

leman

macrumors Core
Oct 14, 2008
19,520
19,670
In an interview with Tom's Hardware, Mark Papermaster, AMD's CTO, explains that the future of AMD chips and look a lot like Apple's Mx: BIG.little hybrid architecture with AI accelerators.

I don't think this is new or surprising. After all, AMD and Intel have been building desktop SoC's for a while now and ML acceleration is pretty much a necessity at this point. And yes, AMD has ben aggressively hiring experts for designing AI accelerators. I personally know someone who was snatched by them right after their PhD.
 

Sydde

macrumors 68030
Aug 17, 2009
2,563
7,061
IOKWARDI
I don't think this is new or surprising. After all, AMD and Intel have been building desktop SoC's for a while now and ML acceleration is pretty much a necessity at this point.

AVX and SVE2 are both constructed to facilitate ML at the CPU level (matrix convolutions). nVidia seems to have something of an edge in this area, though Apple could theoretically advance the ANE to gain some parity. Intel, AMD and ARM seem focussed on advancing CPU capabilities in ML, which may or my not be the ideal strategy.
 

Xiao_Xi

macrumors 68000
Oct 27, 2021
1,627
1,101
AVX and SVE2 are both constructed to facilitate ML at the CPU level (matrix convolutions). nVidia seems to have something of an edge in this area, though Apple could theoretically advance the ANE to gain some parity. Intel, AMD and ARM seem focussed on advancing CPU capabilities in ML, which may or my not be the ideal strategy.
All players seem to be including more and more accelerators. Intel's AVX and SVE2 instructions seem like a stopgap, as Intel now has dGPUs that include specialized matrix multiplication cores. On the other hand, ARM has ML inference processors (Ethos product line) and AMD has included an AI engine in the 7040 series.
 

leman

macrumors Core
Oct 14, 2008
19,520
19,670
AVX and SVE2 are both constructed to facilitate ML at the CPU level (matrix convolutions).

Unfortunately, neither AVX nor SVE are sufficient, since vector SIMD is not the best model for matrix operations. The new state of the art are matrix-specific extensions (Intel AMX and Arm SME) that operate on rectangular registers. I think Apple was the first commercial vendor to ship a matrix engine integrated into the CPU.

nVidia seems to have something of an edge in this area, though Apple could theoretically advance the ANE to gain some parity. Intel, AMD and ARM seem focussed on advancing CPU capabilities in ML, which may or my not be the ideal strategy.

Nvidia is an interesting case. Large matrix convolution (if you are serious about it) requires tremendous memory bandwidth. That's not something CPUs are traditionally known for (which is also why dedicated matrix hardware made such a late debut in the x86 land). But Nvidia put their matmul hardware into a GPU, which already features a huge RAM bandwidth. It's a perfect synergy.

Regarding Apple, they are fairly special because of their unified memory and high RAM bandwidth that is available to all processors. This gives them a lot of flexibility in how they can approach these things. So far their strategy appears to be specialisation. They currently offer four (!!!) hardware types for matrix convolution. One is the plain old CPU SIMD (lowest latency but also lowest performance, best for very small matrix multiplications intertwined with other computation). Then you have the AMX coprocessor which is a dedicated outer product engine fed from the CPU L2 cache and can deliver some very respectable throughput while still being close to the CPU. Then there is ANE, which is a limited function convolution engine specialised for certain type of computation (details seem to be yet unclear), optimised for very low energy consumption. And finally there is the GPU, where SIMD units can be reconfigured to perform a matrix multiplication).

These different devices offer different tradeoffs in terms of energy efficiency, availability, and latency (how quickly the results are available back on the CPU). What's also interesting is that they can be used simultaneously, for a fairly healthy performance boost. From the developer perspective, this is all a bit confusing, and it can be hard to decide which API to use (not that ANE or AMX are directly programmable anyway), but it opens unique perspectives. For example there are reports that Apple does Metal FX resolution upscaling on the ANE, allowing for some truly ridiculous power efficiency.

Folks are often quick to single out the ANE as a counterpart to Nvidia Tensor cores but I don't think this is fitting. ANE will likely continue to be a fairly specialised device, optimised for low-power inference. For general-purpose matrix programming and ML model training both the GPU and the AMX are more interesting IMO. By enhancing their GPU SIMD to support other data formats (e.g. allowing the 32-wide 32-bit SIMD to be reconfigured as 64-wide 16-bit SIMD) and adding some additional matrix-specific ALUs they could match Nvidia's Tensor throughput on core-per-core basis. Of course, Nvidia would still have a massive advance since they can ship many more SMs on a product than Apple can ship GPU cores.
 

leman

macrumors Core
Oct 14, 2008
19,520
19,670
How could it work? Does it mean that the GPU has to send the scene data to ANE and receive it back?

It's all buffers in memory. The upscaling algorithm needs the image data as well as some additional per-pixel information (depth and motion information). The GPU produces this data, the ANE can read it from the memory (or more likely in practice, the shared cache). The resulting image is written back to memory, where it is fetched by the display controller and sent to the video output (display controller is completely different hardware from the GPU and has nothing to do with the later!). And yes, there is some tremendous latency (measured in milliseconds), but it's not really noticeable in practice (no idea, maybe a professional FPS player can perceive an input lag).
 
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diamond.g

macrumors G4
Mar 20, 2007
11,438
2,663
OBX
It's all buffers in memory. The upscaling algorithm needs the image data as well as some additional per-pixel information (depth and motion information). The GPU produces this data, the ANE can read it from the memory (or more likely in practice, the shared cache). The resulting image is written back to memory, where it is fetched by the display controller and sent to the video output (display controller is completely different hardware from the GPU and has nothing to do with the later!). And yes, there is some tremendous latency (measured in milliseconds), but it's not really noticeable in practice (no idea, maybe a professional FPS player can perceive an input lag).
MetalFX (Quality) happens before post processing effects, right? That seems like the latency hit would be high (but not as high as native resolution).
 

Xiao_Xi

macrumors 68000
Oct 27, 2021
1,627
1,101
MetalFX (Quality) happens before post processing effects, right?
1684439308517.png

 

dmccloud

macrumors 68040
Sep 7, 2009
3,141
1,899
Anchorage, AK
It looks like Intel wants to take another page out of Apple's book and wants to simplify x86 ISA to 64-bit only.

Looking over that, I'm not sure it's what people might think at first. We all know that in reality, Intel is currently licensing AMD's 64-bit extensions onto the x86 ISA. However, the article there only mentions "Intel 64" and makes no mention of AMD64/x86-64. They also weirdly claim that "Intel 64" is the dominant operating mode, which is demonstrably false given that Intel is licensing AMDs 64-bit extensions to the x86 ISA as mentioned earlier. Another clue that this is something completely different is in the following paragraph:

While running a legacy 64-bit operating system on top of a 64-bit mode-only architecture CPU is not an explicit goal of this effort, the Intel architecture software ecosystem has sufficiently matured with virtualization products so that a virtualization-based software solution could use virtualization hardware (VMX) to deliver a solution to emulate features required to boot legacy operating systems.

It sounds like Intel is willing (once again) to try to blow up the existing market to implement a new standard it has sole control over.
 
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Bodhitree

macrumors 68020
Apr 5, 2021
2,085
2,216
Netherlands
That’s possible, although I do hope that they will eventually crank up the power consumption. Apple definitely has a lot of headroom compared to the competitors and a faster base Mac Mini/iMac would have so much better value proposition. But then again, the bottleneck still seem to the the supply, so not much point in increasing demand.

What do you base your thinking on for this? It seems to me that Mac Mini / iMac demand is constrained by pricing issues and support for games. Many people I know have a work laptop and a “gaming rig” desktop. And lately we have been seeing great deals for Apple Silicon Mac Mini and iMac on Amazon, signs that Apple isn’t selling all of their inventory at regular prices.
 

name99

macrumors 68020
Jun 21, 2004
2,407
2,309
What do you base your thinking on for this? It seems to me that Mac Mini / iMac demand is constrained by pricing issues and support for games. Many people I know have a work laptop and a “gaming rig” desktop. And lately we have been seeing great deals for Apple Silicon Mac Mini and iMac on Amazon, signs that Apple isn’t selling all of their inventory at regular prices.
"signs that Apple isn’t selling all of their inventory at regular prices."
OR signs that Apple wants to dump that inventory before the M3 stuff (perhaps announced at WWDC) is available? Better to sell it now at $50 lower, than in two months when it has to be $150 lower to compete against M3...
 

dgdosen

macrumors 68030
Dec 13, 2003
2,817
1,463
Seattle
"signs that Apple isn’t selling all of their inventory at regular prices."
OR signs that Apple wants to dump that inventory before the M3 stuff (perhaps announced at WWDC) is available? Better to sell it now at $50 lower, than in two months when it has to be $150 lower to compete against M3...
I wonder if Apple is hedging geopolitical risk... Why not hoard 3nm just in case China does something stupid. Might be prudent risk mitigation.

Hey Apple, just between you and me, I'd gladly pay the Apple tax for a loaded-memory 12" laptop... M1 or M2... Just make it less than 2lb.
 

dmccloud

macrumors 68040
Sep 7, 2009
3,141
1,899
Anchorage, AK
Since RISC-V is developing instructions for interpreted and JIT compiled languages, I can imagine that ARM and x86 ISA have similar instructions.

Is ARM ISA better than x86 ISA for interpreted or compiled JIT languages?

Apple actually has its own set of instructions which run on top of the base ARM ISA (some of which actually have been incorporated into the ARM ISA itself). That's one of the key advantages to the license Apple (and Samsung) have compared to what Qualcomm and others have.
 
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