Even when you run the fans at over 7000RPM to drop the CPU temp by 20 degrees C, the machine doesn't run any faster per Max Tech's testing so I don't believe it is correct to say that the M2 thermally throttles.
As with Max Tech's testing of the entire M1 family, it doesn't looks like Apple allows any M series SoC to draw maximum power (as measured by wattage) to run the clock speed at the maximum rated speed, but instead keeps it a few hundred MHz below that maximum both single and multi core.
Everyone should stop taking Max Tech seriously, they're clowns. They don't know much of anything, they're just good at making slick looking clickbait videos which always amount to a dumbass shouting enthusiastically about things he's misunderstood.
Second, the real thing I wanted to post about is that this behavior where clocks are usually below max rated speed isn't quite what you think. The maximum rated clock frequency is real, but is only available when a single core is active. If two cores are active, another lower limit becomes the max, and if three there might be another limit, etc.
Drilling down a bit, in M1 performance cores are grouped in clusters of four and the performance state of one cluster doesn't affect any other. If I run a single core load on my M1 Max, I see P cluster 0 running at 3228 MHz (the maximum). If I spin up another thread, it drops to 3132 MHz. If I have three or four threads running, it drops to its lowest limit, 3036 MHz. If I add a fifth thread, P cluster 1 comes online and runs at 3228 MHz while P cluster 0 continues to run at 3036.
This kind of thing is a common pattern in modern high performance chip design. Using the obvious example, it's present to a much greater degree in Intel products. It's not exclusively about thermals either; for M1 I'd guess it's more about electrical power distribution. Each core consumes quite a lot of electrical current at high power states, and that produces I*R voltage droop in the chip's power distribution network. Droop means the power supply voltage observed at gates located in the middle of dense high power areas is depressed quite a bit; if you let this go too far some gates will have supply voltage dip too low for correct operation. Managing voltage droop is important, and one way of doing it is to restrict clocks a bit when multiple copies of a high performance, high power block that are physically laid out next to each other are all active at the same time.