Hard Truths About The Apple Silicon Replacement to the Mac Pro (2019)

[Jack Burton]

What matters more: having the ability to upgrade chips and RAM for a few years (remember, the CPU socket goes obsolete at some point too) or saving massive amounts of time during the workflow which lets you iterate/work faster? I literally don't know anyone that picks the former for professional work.

I like this thinking.

Is the rumor that the MacPro will have the same chipsets as the Mac Studio (M2/3 max/ultra?) If so, I can't imagine the mac pro saving me enough time to make a price premium above the studio max/ultra to be worth it.

Modularity now, for me, exists only for video cards on the PC. And is it really modular if I need a new case/power supply, cooling etc when a new video card launches?

Need more computer power? You'll be offloading those tasks to the cloud sooner than later, that's infinite upgrade power that never goes obsolete.

I believe there is a LOT of truth to this. It's one of the reasons the mac studio is appealing to me: the rise of cloud rendering for long animations/videos.

Why worry about crashes, power failures/flickers, heat, power bills, etc using my local machine?


What a 180 I've done in the past 10 years or so. You guys have made me think. A few years back I never thought I'd be skeptical about needing a mac pro or monster PC.

 

[deconstruct60]

Let's get real: using a PCI slot just for storage expansion would be a waste in almost all scenarios (not all, but almost all). Chances are that USB 3.0 / Thunderbolt 3 / Thunderbolt 4 would satisfy the needs for storage upgrades with external disks,

In 3-4 years when PCI-e v5 M.2 SSDs are relatively far more commonplace. That won't be true.

Corsair Teases First PCIe 5.0 SSD With 10,000MB/s of Bandwidth

New PCIe 5.0 SSD could drop this year

www.tomshardware.com

Right there is a simple prototype that 'blows up" TBv4 bandwidth: completely swamped ( peak 80 vs 40 ). By 2nd or 3rd generation of these x4 PCI-e v5 backbone drives, they too are going to outclass TBv5. And all you need is just two drives to certainly crush TB v4 or 5 bandwidth. In the Mac Pro class folks only use two drives? If need 10's of TB of capacity and high write actions over a long period of time , then going to need more than just two drives.

Even Apple explicitly admitted that having one , and only one, internal drive coupled with leaning "too hard" on Thunderbolt doesn't work in Mac Pro space. Thunderbolt 4 and 5 doesn't really change that at all because the mid-high storage space is getting faster and larger over time also. For most mainstream users ? Yes , things are plateauing. For a larger portion of "enthusiats class". Yeah two, x4 PCI-e v4 drives is going to cover lots more territory.

But at the price points that Apple is confined the Mac Pro to ( > $5K ) the shallow end of the mainstream pool largely isn't who they are selling systems to. Apple's non competitive prices on 8TB drives only reinforces that weakness. For folks that need 10-40TB of storage Apple's prices don't make sense (and Apple can't cover the capacity anyway).


And for folks looking for racked systems. They'll want the 'back end' storage neatly, efficiently racked into the system also. ( you can 'make' TBv4 work for that but it isn't the neatest or most efficient solution. ]

and you can mitigate speed issues to a degree with an Ethernet cable / RAID setup.

If want to do a very good job at mitigating transfering terabytes of data quickly then 10GbE isn't going to cut it. Which again if talking high performance SAN/NAS solution means buying a PCI-e card to do better than 10GbE to get it done. Effectively, yes have used something better bandwidth than TBv4 to solve the problem.

 

[mr_roboto]

The usual rule of thumb is that the power scales as the square of the clock speed, rather than exponentially (and it should be acknowledged sam_dean didn't say exponentially either). We can use this to roughly predict the power draw at higher clocks.

This is not correct. To see why I'm going to walk you through the basics of CMOS power.

Ideal CMOS logic uses power only in the instant that gates and wires change state (0 to 1 or 1 to 0); in the static condition when nothing is happening, supply current drops to 0.

Every clock edge causes some percentage of the gates and wires in the chip to change state. Each one of these flips means a tiny capacitance got charged or discharged.

The energy stored in a fully charged capacitor is 0.5*C*v^2, where C is the capacitance and v is the supply voltage. Takes the same energy to charge it to full or discharge to empty. If the average number of bit flips due to a clock edge is N, that gives the total energy dissipation of each clock edge as N*0.5*C*v^2.

Power is energy per unit time, so if we just multiply the number of clock edges happening per second - aka the clock frequency - by the above equation we get power. If we want to just think about the effects of voltage and frequency, we arrive at saying that power is proportional to f * v^2.

There's all sorts of simplifying assumptions buried in everything I've said. However, it's broadly true.

Now, do you have to raise voltages to hit higher frequencies? You do. Do you have to raise voltage at a rate where power actually begins to scale as the square of frequency? No, typically not.

A lot depends on where you're starting from on the voltage vs frequency curve. Apple likes to run their chips down in the efficient regions of the curve, closer to Vt (threshold voltage, which is roughly the minimum voltage at which the chip can operate). Down there, it doesn't take much of a voltage bump to greatly increase frequency. Intel's pushing frequency to the limit, so they're up in the inefficient regions where it takes a lot of voltage to get the same frequency gains.

According to https://www.notebookcheck.net/Apple-M2-Max-Processor-Benchmarks-and-Specs.682771.0.html:

"When fully loading the CPU and GPU cores, the chip uses up to 89 Watt and the CPU part is limited to 25 Watt."

Thus we can estimate that, for the CPU, 25 W@3.7 GHZ for the Max would extrapolate to the following for higher-clocked M2 Ultras (I multipled by two to go from the Max to the Ultra):
25 W x (4.2/3.7)^2 x 2 = 64 W @ 4.2 GHz
25 W x (4.5/3.7)^2 x 2 = 74 W @ 4.5 GHz

So if it really is quadratic (increases as the square of the frequency), the difference between 50W for a 3.7 GHz M2 Ultra, vs. about 65W – 75 W for higher-clocked variants, would seem to be trivial for a Mac Pro.

Even if the increase is stronger than quadratic, we're still probably under 100W even at the higher clock speed. That is significantly lower than the power budget of even the least powerful CPU that goes into the current Mac Pro case, the 3.5 GHz 8-Core Xeon W (W-3223), whose nominal TDP is 160W.

So, for an M2 Ultra in the current Mac Pro case, the limit on scaling to higher clocks should depend solely on the limits of the M2 chip itself.

Rethink what you've tried to do here in light of what I've said. You simply can't try to confidently predict power changes based on frequency without knowing a lot more data. Mainly the voltages required to make Apple's design function correctly at 3.7, 4.2, and 4.5 GHz, but also there's a whole lot of other things which go into the mix. (e.g. one choice designers often face when choosing to optimize a chip design for efficiency vs power is that, at least a few nodes ago, and probably still now, you can choose to have faster but leakier transistors or slower and less leaky. Leakage is not something I covered above at all, and it matters a whole lot, because real CMOS logic is not perfect. It uses power all the time rather than just when a clock edge triggers a cascade of bit flips.)

 

[Mago]

M2 Max has provisions for not One but: Two ultrafusion.

Maybe serial stackable in 1,2,3...4? "Sockets" plus a mega I/o phy.

So the m2 Mac pro cpu complex likely to look like this:

  SSD «» [PHY I/O] «» (mux) PCIe5 ... 4, usb4
           (UF+)
Ram (RCD) [M2 Max] (RCD) Ram
           (UF+)
Ram (RCD) [M2 Max] (RCD) Ram
           (UF+)
Ram (RCD) [M2 Max] (RCD) Ram
           (UF+)
Ram (RCD) [M2 Max] (RCD) Ram

RCD: registering clock driver

UCIe (apple is buying)

I'm leaving it here while slowly I leave the room...

Those not aware my other thread's comments, dont give a thing on Gurman Letters, mostly imagination or false cues implanted by Apple.

The Mac Pro 8,1 ASi, to be availlbe witth 1,2,3,4 M2 Max Configurations, Discreet Ram Modules (DIMM, SO-DIMM or whatever) upto 4TB (for those with enough pockets for it), at least 2 PCIe% x16 and 5 other Slots PCIe4 x16 or x8 even maybe x8 Pcie5.

Dont Worry about GPU, the ASi Mac Pro wont dissapoint.

As about the Cheese Grater Chasis, nothing safe but likely to keep it unchanged, but the new Internals actually requires abour 20% less height.

M2 Mac Studio likely to be available with M2 Max and Dual M2-Pro "ultra".

 

[mr_roboto]

M2 Max has provisions for not One but: Two ultrafusion.

Correction: M2 Max has unknown provisions for Ultra Fusion. Everything in what you posted is just your speculation.

 

[sam_dean]

Correction: M2 Max has unknown provisions for Ultra Fusion. Everything in what you posted is just your speculation.

I have yet to see any exposed M2 Max die from any professional reviewer or actual user.

So it is speculation as of now that there is more than 1 provision for UltraFusion.

If there is more than 1 Ultrafusion then a four die M2 Max may look similar to this.

A four die M2 Max would have 4x of everything a M2 Max would have.

It is likely placed only in a future 2023 Mac Pro as it would require >400W of power and a logic board that could only fit in a tower with PCIe expansion slots.

That four die M2 Max would sell for around $10k based on the price increments of a $2k Mac Studio M1 Max to $4k M2 Ultra and the $2k premium of a Mac Pro base model.

 

[Mago]

If there is more than 1 Ultrafusion then a four die M2 Max may look similar to this.

Wrong, m2 Max UF+ is at top and bottom, a 4 Way m2 extreme would look like stacked over each other, not That table like arrangement, it's also is consistent with ram interface at each processor side, that design isn't New Intel adopted it at some xeon-phi implementations sharing a fabric interconnect.
M2 Modular (aka extreme) should be available in 1p,2p,3p & 4 p configuración, UltraFusion+ BW likely 2.25 more then m1 ultra.
The M2 Mac pro to include discreet DDR5 ram modules Apple signed for the required IP for the components required.
Only puzzle part is the GPU Apple may develop it's own dGPU on 'defective ' m2 chips with disabled cores and custom firmware, or just enable new AMD GPU drivers, m2 Max/m2 modular x4, has no competitive GPU power compared with STD workstation GPUs, so unlikely apple not to provide an solutions.

 

[sam_dean]

Wrong, m2 Max UF+ is at top and bottom, a 4 Way m2 extreme would look like stacked over each other, not That table like arrangement, it's also is consistent with ram interface at each processor side, that design isn't New Intel adopted it at some xeon-phi implementations sharing a fabric interconnect.
M2 Modular (aka extreme) should be available in 1p,2p,3p & 4 p configuración, UltraFusion+ BW likely 2.25 more then m1 ultra.
The Mac Mac pro to include discreet DDR5 ram modules Apple signed for the required IP for the components required.
Only puzzle part is the GPU Apple may develop it's own dGPU on 'defective ' m2 chips with disabled cores and custom firmware, or just enable new AMD GPU drivers, m2 Max/m2 modular x4, has no competitive GPU power compared with STD workstation GPUs, so unlikely apple not to provide an solutions.

!Remind me January 2024.

Your limitation of having UltraFusion at the top & bottom of each M2 Max chip would be the 300mm silicon waffer.

Is there space enough for four M2 Max chips staked on top of each other?

 

[theorist9]

This is not correct. To see why I'm going to walk you through the basics of CMOS power.

Ideal CMOS logic uses power only in the instant that gates and wires change state (0 to 1 or 1 to 0); in the static condition when nothing is happening, supply current drops to 0.

Every clock edge causes some percentage of the gates and wires in the chip to change state. Each one of these flips means a tiny capacitance got charged or discharged.

The energy stored in a fully charged capacitor is 0.5*C*v^2, where C is the capacitance and v is the supply voltage. Takes the same energy to charge it to full or discharge to empty. If the average number of bit flips due to a clock edge is N, that gives the total energy dissipation of each clock edge as N*0.5*C*v^2.

Power is energy per unit time, so if we just multiply the number of clock edges happening per second - aka the clock frequency - by the above equation we get power. If we want to just think about the effects of voltage and frequency, we arrive at saying that power is proportional to f * v^2.

There's all sorts of simplifying assumptions buried in everything I've said. However, it's broadly true.

Now, do you have to raise voltages to hit higher frequencies? You do. Do you have to raise voltage at a rate where power actually begins to scale as the square of frequency? No, typically not.

A lot depends on where you're starting from on the voltage vs frequency curve. Apple likes to run their chips down in the efficient regions of the curve, closer to Vt (threshold voltage, which is roughly the minimum voltage at which the chip can operate). Down there, it doesn't take much of a voltage bump to greatly increase frequency. Intel's pushing frequency to the limit, so they're up in the inefficient regions where it takes a lot of voltage to get the same frequency gains.

One of my mentors was fond of paraphrasing Einstein as follows: "You want your model to be as simple as possible, but not too simple." And how simple your model can be depends on its intended use. Note that my purpose here was not to precisely predict the TPD's of the M2 Ultra at those higher frequencies, but rather to be predict whether or not the current Mac Pro case has sufficient TDP to handle an M2 Ultra pushed to those frequencies (if this could be done with the Ultra). I.e., I just needed to determine a very rough upper bound, and see if that was significantly lower than the TDP's of the chips used in the Mac Pro. And for that, my model may be sufficient. But it's certainly possible I went overboard in my coarse graining, even for my very simple purposes. [Though I don't think I was quite at the point of "imagine a spherical cow..."]

My simple estimate that P ~ f^2 was based on this discussion:

https://forums.macrumors.com/threads/what-microarchitecture-choices-have-made-m2-less-efficient-than-m1.2352555/page-5?post=31303963#post-31303963

Rethink what you've tried to do here in light of what I've said. You simply can't try to confidently predict power changes based on frequency without knowing a lot more data. Mainly the voltages required to make Apple's design function correctly at 3.7, 4.2, and 4.5 GHz, but also there's a whole lot of other things which go into the mix. (e.g. one choice designers often face when choosing to optimize a chip design for efficiency vs power is that, at least a few nodes ago, and probably still now, you can choose to have faster but leakier transistors or slower and less leaky. Leakage is not something I covered above at all, and it matters a whole lot, because real CMOS logic is not perfect. It uses power all the time rather than just when a clock edge triggers a cascade of bit flips.)

Your response seems somewhat off-point, since I wasn't "confidently predicting" the TDP's of the chip at higher frequencies. That's a straw man, since I explicitly said these were very rough estimates. Rather the only thing I did confidently predict, which was the heart of what I wrote, and that you didn't address, is that is that, if the M2 Ultra can be pushed to 4.2–4.5 GHz, the current Mac Pro case is highly likely to have enough thermal dissipation capacity to handle it. Do you disagree?

This is not correct. To see why I'm going to walk you through the basics of CMOS power....Rethink what you've tried to do here in light of what I've said.

Finally, I'd appreciate a more friendly and collegial tone. You've given me corrections in the past, but they've always been much more collegial. And in every case (or nearly so) I've given the post a "like" and also typically responded with a "Thanks for the correction!" or the equivalent, because I appreciated the time you took, the info. you imparted, and the collegial tone. But this, by contrast, seems lecturing and condescending. For instance, in the following case, where you got something wrong in my field, I could have taken the same tone, but did not. Note I didn't say "I'm going to walk you through the basics of chemistry" or "Rethink what you've tried to say here in light of what I've said", since those comments would have been gratuitous.

 

[Mago]

!Remind me January 2024.

Your limitation of having UltraFusion at the top & bottom of each M2 Max chip would be the 300mm silicon waffer.

Is there space enough for four M2 Max chips staked on top of each other?

FYI Apple Silicon chipsets aren't monolithic chips, are individual chips taken even from different waffers, do yourself a favor, Google UltraFusion https://apple.fandom.com/wiki/UltraFusion
Clearer here

The Tech Behind Apple's M1 UltraFusion Chip Interconnect

TSMC's CoWoS-S in action

www.tomshardware.com

Apple UltraFusion+ is using TSMC's InFO_LS not CoWoS-S (as maybe m1' UF), the main reason we haven't an m1 extreme Mac pro

Nothing New Intel did it with xeon-phi knightslanding.

Why Jan 2024? The new modular Mac is on schedule for 23' WWDC.

PD: everything I wrote comes from my imagination fueled by beers, pot and unhealthy food, any coincidence with reality it's just luck (o/ hi Apple Legal).

 

[mr_roboto]

Finally, I'd appreciate a more friendly and collegial tone. You've given me corrections in the past, but they've always been much more collegial. And in every case (or nearly so) I've given the post a "like" and also typically responded with a "Thanks for the correction!" or the equivalent, because I appreciated the time you took, the info. you imparted, and the collegial tone. But this, by contrast, seems lecturing and condescending.

I apologize. Was in a bad mood, saw a long post which seemed to be about attempting to calculate real numbers based on a bogus equation, and reacted to that without reading thoroughly for context.

I do agree that if M2 Max/Ultra actually can be pushed to 4.5 GHz (which is by no means certain), the existing Mac Pro chassis would be more than adequate. If it's not, Apple's in trouble, as the 2019 Mac Pro is already capable of pulling somewhere around 1kW continuous, and that's getting very close to the limits of what you can do through a NEMA 5-15 power receptacle at 115 VAC (the standard US office power source).

 

[Nudelpalm]

I am in no way knowledgeable in the specifics on how a computer work, but would it make sense for Apple to release PCIe-cards containing extra RAM?

 

[leman]

I am in no way knowledgeable in the specifics on how a computer work, but would it make sense for Apple to release PCIe-cards containing extra RAM?

Not really. PCIe is very slow compared to RAM interfaces. From what I understand, you could get to 100GBs or so with 32 lanes of PCIe5 (the latency will probably be not very good though), which would be a very expensive and a rather slow solution. This could make sense as an additional layer between the main RAM and the primary storage but hardly as a system RAM extension. (edit: see below)

Then again there are research initiatives like CLX.mem, so maybe it is feasible. A couple of 16x CLX 3.0 links could add up to a reasonable bandwidth and I suppose the protocol has provisions to reduce the latency. But quite honestly, I don't really see much advantage in going that route for the Mac Pro. If Apple is prepared to go though so much trouble they could simply support regular DDR5 as "external" RAM tier.

Edit: actually, your question prompted me to read more about CLX-based memory expansions. Various sources claim that the latency of existing prototypes is in the ballpark of 200ns, which is perfectly fine for second-level RAM. It might very well be a reasonable solution for a Mac Pro. Would be interesting to know whether Apple is getting involved with the CLX stuff. At any rate, they are not listed as a member of CXL Consortium.

 

[Nudelpalm]

Not really. PCIe is very slow compared to RAM interfaces. From what I understand, you could get to 100GBs or so with 32 lanes of PCIe5 (the latency will probably be not very good though), which would be a very expensive and a rather slow solution. This could make sense as an additional layer between the main RAM and the primary storage but hardly as a system RAM extension. (edit: see below)

Then again there are research initiatives like CLX.mem, so maybe it is feasible. A couple of 16x CLX 3.0 links could add up to a reasonable bandwidth and I suppose the protocol has provisions to reduce the latency. But quite honestly, I don't really see much advantage in going that route for the Mac Pro. If Apple is prepared to go though so much trouble they could simply support regular DDR5 as "external" RAM tier.

Edit: actually, your question prompted me to read more about CLX-based memory expansions. Various sources claim that the latency of existing prototypes is in the ballpark of 200ns, which is perfectly fine for second-level RAM. It might very well be a reasonable solution for a Mac Pro. Would be interesting to know whether Apple is getting involved with the CLX stuff. At any rate, they are not listed as a member of CXL Consortium.

I’m just glad I wasn’t totally on the wrong!

 

[leman]

I’m just glad I wasn’t totally on the wrong!

No, not at all! Not being an expert in a certain field often allows one to have a perspective that someone who tends to get stuck in technical detail will miss. When one things about it logically, RAM expansion via regular device slots makes total sense. It's just that until very recently, the technology wasn't mature enough. Compute Express Link is a very recent initiative that only now starts being adopted in actual hardware.

That said, I have my doubts whether Apple will be using CLX. They are not really interested in server interoperability technology and they are big enough to have their own custom solutions. There is also no information whatsoever that would suggest that Apple pursues CLX-based solutions.

 

[SlCKB0Y]

1. The RAM will not be separately user-upgradeable; it will be tied to the SoC.

2. There will be no PCIe GPU nor eGPU upgradability or expansion; the only GPU will be the one on the SoC.

Before anyone challenges me with that, make sure you have watched this video from WWDC 2020 (where the Intel to Apple Silicon transition was first announced): https://developer.apple.com/videos/play/wwdc2020/10686/ (at about the 1-minute mark)

Nothing in that video PRECLUDES the future possibility of having expanded, slower, tiered memory off the SoC. It only speak to the benefits in 2020 of having on-package memory.

I'm not saying they will do it, but the logic of what was stated in the video is not definitive either way.

 

[diamond.g]

Nothing in that video PRECLUDES the future possibility of having expanded, slower, tiered memory off the SoC. It only speak to the benefits in 2020 of having on-package memory.

I'm not saying they will do it, but the logic of what was stated in the video is not definitive either way.

It would be interesting to see if Apple offers slower memory and leaves the faster RAM as a L4 cache or if they will allow it to be accessed like the slower RAM pool. That would/could cause a programming model difference between Apple Silicon differences, no?

 

[leman]

It would be interesting to see if Apple offers slower memory and leaves the faster RAM as a L4 cache or if they will allow it to be accessed like the slower RAM pool. That would/could cause a programming model difference between Apple Silicon differences, no?

If Apple offers a tiered memory solution it will almost certainly be completely transparent to the application. I can maybe imagine some RAM prefetch hints, but that's it.

Edit: it seems that RAM prefetch hints have been implemented in macOS around 20 years ago as part of the posix APIs. So we are all set on that side

 

[Spindel]

I've said it many times before in threads like these and I'll say it again.

I strongly believe that a Mac Pro will have UMA and RAM slots. But the RAM in the slots should be viewed more as a fast swap pool than RAM in the traditional sense.

Current AS CPUs are basically tiered as following:

On die cache -> SoC RAM -> SSD Swap

So three tiers, my belief for the Mac Pro is:

On die cache -> SoC RAM -> traditional RAM modules Fast Swap -> SSD Swap

 

[JouniS]

I strongly believe that a Mac Pro will have UMA and RAM slots. But the RAM in the slots should be viewed more as a fast swap pool than RAM in the traditional sense.

I don't think that would be a good idea. If you make weird hardware, you are effectively telling everyone not to optimize their software for your hardware.

Even Intel CPUs are so weird that software is rarely optimized for them. Most of the performance is hidden behind obscure SIMD instructions that do not correspond well to operations available in widely used programming languages. Because using those SIMD instructions effectively is so difficult and time-consuming, even people who care about performance rarely take proper advantage of them.

Widely used programming languages assume that the computer has RAM that can be addressed. The contents of the RAM can be cached transparently for lower access latency. They can also be swapped out and in transparently to extend capacity, but that tends to increase latency greatly. If this is not a good model for your hardware, that's your problem. By making weird hardware, you are actively wishing for poorly optimized software.

In applications that require a lot of RAM, the number of CPU cores divided by memory latency is often a good first approximation for performance. CPU speed does not matter much, because the CPU is just waiting for memory access most of the time. If Apple chooses to use slotted RAM as swap, the new Mac Pro is going to be slow in this kind of applications.

 

[fuchsdh]

Top of the market wants to optimize for time and productivity, productivity that increases as a result of saving time (theoretically). Apple are banking on Apple Silicon to be so fast and efficient for core industry workflows (video editing, coding, audio production, design work, etc.) that most professionals will consider nothing but Apple Silicon Macs for their workflows. That already happened in the startup world even before Apple Silicon came along despite being held back by space heater Intel chips. Find me a hot new piece of software for professional productivity that doesn't release on Mac first (well, Mac second. Most are web first these days I guess). What matters more: having the ability to upgrade chips and RAM for a few years (remember, the CPU socket goes obsolete at some point too) or saving massive amounts of time during the workflow which lets you iterate/work faster? I literally don't know anyone that picks the former for professional work.

I think the secret second reason is a bit more subtle. Apple probably don't mind alienating the 0.1% of people that really REALLY need the specific benefits of Mac Pro's modular design because they care more about capturing the younger creator market instead. They want kids to grow up using iPhones and Macs to create content and their first apps so that when they get older and make their own companies they're already embedded into the Apple workflow. Kids don't care about modularity, they just care about saving time (AirDrop saves time. ProRes encoders for video editing saves time. iMessage on Mac saves times. The list goes on). Same goes for working professionals too in most scenarios. I'm in both categories.

Modular/upgradable Macs are fully done. OP got it right, the most we'll see are PCIe slots for esoteric coprocessing units or domain specific I/O. I wouldn't be surprised at all if most Mac Pro buyers from the current generation didn't upgrade their Macs at all beyond adding something to a PCIe slot like an Afterburner card.

I'll go a step further in saying I think the Mac Pro line is dead, unless they decide to make that special 4x Max chip but that got cancelled. The next gen Mac Pro will only be useful for I/O upgrades. Once advancements in USB reach the point of no longer needing PCIe I/O cards, what next? Need more computer power? You'll be offloading those tasks to the cloud sooner than later, that's infinite upgrade power that never goes obsolete. Only a matter of time before people don't even bother buying top of the line chips anymore because the benefits of cloud first workflows outweigh the benefits of getting a super impressive local chip.

GitHub Codespaces are a premonition.

People have been swearing that the days of a powerful big dumb computer at your desk are over for years (decades, if you want to count the network computers people tried to make A Thing), and that hasn't been borne out. As fast as Thunderbolt and USB get, they're still much slower than what PCIe can do, and as fast as internet speeds are they don't beat local DAS or NAS speeds. Lots of people can get by with thin clients, but there's still always going to be the next hefty, power-hungry task; as one's tools improve, so do standards.

This doesn't mean Apple is going to compete in that segment, but we've seen how the workstation is actually a growing market segment. Reports of its death are greatly exagerrated. The question is whether that market is now totally orthogonal from the rest of Apple's lineup.

 

[sam_dean]

I am in no way knowledgeable in the specifics on how a computer work, but would it make sense for Apple to release PCIe-cards containing extra RAM?

It would increase cost, power consumption, latency and introduce a redesign that would solely cater Mac Pro desktop users that want PCIe expansion slots.

Mac Pro desktop users have been split into those who want to pay for PCIe expansion slots and those who do not.

As evident to how frequently the Mac Pro was updated without PCIe expansion slots tells me that >50% of Mac Pro users prefer a design like the Mac Studio.

What does this mean to Mac Pro buyers? Economies of scale will be worse for this product line as the volume is reduced by over half unless it offers a two die M2 Ultra chip exclusive to the Mac Pro.

Any Pro desktop user who wants a two die M2 Ultra with 48-core CPUs will have to buy that.

My guestimate price for that SKU would start at $9999. Not bad for a business expense when time is money.

Odds are the power consumption without any use of expansion slots would fall below 300W even when the PSU may continue to be 1,500W.

 

[sam_dean]

This doesn't mean Apple is going to compete in that segment, but we've seen how the workstation is actually a growing market segment. Reports of its death are greatly exagerrated. The question is whether that market is now totally orthogonal from the rest of Apple's lineup.

I am having difficulty googling the annual worldwide shipment figures for workstations. Would you mind sharing them?

I suspect that it may have stagnated...

 

[leman]

I don't think that would be a good idea. If you make weird hardware, you are effectively telling everyone not to optimize their software for your hardware.

Even Intel CPUs are so weird that software is rarely optimized for them. Most of the performance is hidden behind obscure SIMD instructions that do not correspond well to operations available in widely used programming languages. Because using those SIMD instructions effectively is so difficult and time-consuming, even people who care about performance rarely take proper advantage of them.

Widely used programming languages assume that the computer has RAM that can be addressed. The contents of the RAM can be cached transparently for lower access latency. They can also be swapped out and in transparently to extend capacity, but that tends to increase latency greatly. If this is not a good model for your hardware, that's your problem. By making weird hardware, you are actively wishing for poorly optimized software.

In applications that require a lot of RAM, the number of CPU cores divided by memory latency is often a good first approximation for performance. CPU speed does not matter much, because the CPU is just waiting for memory access most of the time. If Apple chooses to use slotted RAM as swap, the new Mac Pro is going to be slow in this kind of applications.

I think what was meant by “RAM as swap” is that they add a level of slower expandable RAM. The fast on-package RAM could be considered side-cache to that big slower RAM or that RAM would be considered as a backing store for the fast RAM - that becomes more of a rhetorical matter. The main point is that this would be handled by the memory controller in a manner that’s entirely transparent to the software. Imagine additional six channels of DDR5 backing the current DRAM interface, that’s 300GB/s - faster than a PCIe GPU bus. You can have a huge working memory pool without losing the benefit of a fast unified memory.

Also, I’d disagree with your example of SIMD as being “weird”. It’s a solution to a very different problem. And it’s being aggressively used by software - where appropriate. All these partially redundant blocks and features might seem weird and hard to use but they are there for a reason. I mean, Apple offers at least four different hardware blocks to perform matrix operations, each of them optimized for a different purpose and each of them useful in its own way.

 

[leman]

Mac Pro desktop users have been split into those who want to pay for PCIe expansion slots and those who do not.

As evident to how frequently the Mac Pro was updated without PCIe expansion slots tells me that >50% of Mac Pro users prefer a design like the Mac Studio.

I think you forgot that the only Mac Pro without internal expansion is widely considered a commercial failure and Apple themselves have admitted that it was not successful. Mac Studio/iMac Pro class devices have their place and it is indeed possible that most enthusiast Mac users are satisfied with them, but it’s not what a potential Mac Pro user is looking for.