i hope intel comes back to beat the m1

[crazy dave]

That would be no more performant than just having triple the number of ice storm cores. You wouldn’t improve “single core” performance that way, only multi-core performance (and single core performance would go way down). And since multi-core performance = single core performance times the number of cores (more or less), you’d be lowering multi-core performance unless you increased the number of cores a lot.

The difference between fire and ice-storm is very different than having three cores-in-one vs not.

Aye, I recognize that. My thinking was something akin but different from bulldozer which is maybe not a great idea - or maybe more akin to an inverted bulldozer where instead of shared computational resources among cores it would be a single, segment-able core such that parts of it could fused off, shut down, or run smaller tasks separate from the rest of the core segments rather than literally x Icestorm cores - ie take the superscalar aspect of the big core and be able to break that into effectively smaller cores with less width. So you’d still have a full firestorm-like core to start with but the parallel execution units and pipelines can be fully segmented. Of course your point that there is more to a low power core than just having lower clocks and less width is absolutely true. It was just one of those hairbrained could-you-build-such-a-thing ideas.

 

[cmaier]

Aye, I recognize that. My thinking was something akin but different from bulldozer which is maybe not a great idea - or maybe more akin to an inverted bulldozer where instead of shared computational resources among cores it would be a single, segment-able core such that parts of it could fused off, shut down, or run smaller tasks separate from the rest of the core segments rather than literally x Icestorm cores - ie take the superscalar aspect of the big core and be able to break that into effectively smaller cores with less width. So you’d still have a full firestorm-like core to start with but the parallel execution units and pipelines can be fully segmented. Of course your point that there is more to a low power core than just having lower clocks and less width is absolutely true. It was just one of those hairbrained could-you-build-such-a-thing ideas.

But that’s what already happens (if I understand what you are saying). In firestorm, each pipeline is almost certainly in a separate power domain and is shut off when not in use. That’s how almost any superscalar design works, nowadays.

 

[crazy dave]

But that’s what already happens (if I understand what you are saying). In firestorm, each pipeline is almost certainly in a separate power domain and is shut off when not in use. That’s how almost any superscalar design works, nowadays.

Oh cool. Didn’t know that. Makes sense though. I think the one additional part to the idea is to then also take the pipelines not in use and let them run additional threads. I realize as I’m typing this that I’ve just reinvented SMT, but it would be different from SMT in that they could fuse off their core resources - so that it wouldn’t have all the security concerns of SMT and be more flexible. It would be effectively like it’s own mini core.

 

[cmaier]

Oh cool. Didn’t know that. Makes sense though. I think the one additional part to the idea is to then also take the pipelines not in use and let them run additional threads. I realize as I’m typing this that I’ve just reinvented SMT, but it would be different from SMT in that they could fuse off their core resources - so that it wouldn’t have all the security concerns of SMT and be more flexible. It would be effectively like it’s own mini core.

You can’t really do that because each thread needs its own register contents. So if you have N-different threads running, you’d need N-copies of the register file, each with different contents. You’d then need N-different register renaming units, etc. You end up with, essentially, N-different cores. At least with SMT, you only need one set of register contents at a time.

 

[crazy dave]

You can’t really do that because each thread needs its own register contents. So if you have N-different threads running, you’d need N-copies of the register file, each with different contents. You’d then need N-different register renaming units, etc. You end up with, essentially, N-different cores. At least with SMT, you only need one set of register contents at a time.

Yeah that’s where I thought the idea might fall down ... how many redundant resources would you need to make this work to the point where it wouldn’t really be worth it.

 

[Sydde]

You can’t really do that because each thread needs its own register contents. So if you have N-different threads running, you’d need N-copies of the register file, each with different contents. You’d then need N-different register renaming units, etc. You end up with, essentially, N-different cores. At least with SMT, you only need one set of register contents at a time.

A functional register file for a PE is a little under 1K when you include the various system level registers. That seems like a pretty small footprint in the scheme of a core's logic. I was not advocating for divisible cores, though, as the cost/benefit seems a little on the high side.

 

[cmaier]

A functional register file for a PE is a little under 1K when you include the various system level registers. That seems like a pretty small footprint in the scheme of a core's logic. I was not advocating for divisible cores, though, as the cost/benefit seems a little on the high side.

You would need to duplicate not just the register file, but all the bypass logic, etc. You’d also have to multiplex every input to each ALU to accept from multiple register files. And you would need to vastly complicate, and possibly replicate, the scheduler and register renaming logic, including the CAMs. In the grand scheme of things it’s not much, but it would blow up the size of the scheduler unit, the integer execution units, and possibly other units as well. (I haven’t even considered what happens to the load/store logic in this scheme).

 

[Sydde]

I haven’t even considered what happens to the load/store logic in this scheme

Oh, come on, man, did you not work on this stuff at AMD when they were doing HT? It is fundamentally the same idea. ARM seems to show that the efficiency yield on OoOE is better than that of HT.

 

[cmaier]

Oh, come on, man, did you not work on this stuff at AMD when they were doing HT? It is fundamentally the same idea. ARM seems to show that the efficiency yield on OoOE is better than that of HT.

Huh? I‘m not sure what you are asking. This idea is not fundamentally the same as HT, for the reasons I’ve mentioned. And I’m not sure why you raise your last point, as it seems irrelevant to this issue.

 

[SlCKB0Y]

You can be a little nicer on your correction, you go WAY too far into attack territory, but anyway I stand corrected. If you'll look at my phrasing, you can see I was guessing and just stating an opinion from what I see. (I don't work on the provider side, I'm on the other side of the equation.)

And also fwiw, I go back to the middle 70's with computers, and we did have real "mainframes" back then sitting in the big data centers -- it was before the PC architecture was even born. (IBM 360, 370's and lots of other kinds)

I certainly apologise for the harshness of my response. Having re-read it I certainly could have corrected you in a more respectful manner.

 

[bobcomer]

I certainly apologise for the harshness of my response. Having re-read it I certainly could have corrected you in a more respectful manner.

Apology gladly accepted!

 

[sstreky]

I get what the OP's feeling is here, that competition is good. And it is. Wherever there is no competition, either by lack of a competitor market or by government squashing the competitor market (public utilities, anybody?), less competition always discourages innovation. What's left is products or services that are unreliable, expensive, or just plain not relevant.

Examples can be found in a number of industries now: Taxi services have to compete with people who have a car and want to drive other people around for a fee. And just for an hour or two because we have to pick up the kids later from soccer and violin practice. Taxi services, particularly in the large cities, were noncompetitive, expensive, and full of fraud.

Another example is the US Postal Service. Now with UPS, FedEx, and other shippers, the USPS has had to get off their high horse and consider Sunday service. And Amazon, the biggest worldwide shipper now, has insourced that service. And mostly my stuff comes FAST. With USPS, I have to go to the mailbox. Or to my neighbors, since there's a super high rate of misdeliveries with the USPS. But with Amazon, my potholders, vacuum filters, and trinket deliveries always end up on MY porch (at least until my porch pirate decides to risk getting shot in my neighborhood and tries to steal them).

Even in the aerospace, space satellite, and defense industries, we have new players tipping over the applecart of the 100 year old companies.

This is all good.

But!

Just saying that the M1 needs a competing chip? Well on the surface that sounds great, but it's also missing a big component of the discussion here. Intel's "product" is the chip, yes. But Apple's product is not just "a chip". For Apple, it is the combination of the hardware package (of which the chip is only one part), combined with the software.

Apple is selling an EXPERIENCE, whereas everybody else is selling a widget.

Apple saw this with the original Motorola Mac, and wanted to IMPROVE THE PRODUCT (not just the chip) by improving the chip. Hence the move from IBM to Intel. But then AGAIN, the chip technology for the Mac was found to be lagging. This time, however; instead of moving to another chip supplier, Apple decided to source from a proven, reliable, and innovating chip provider: Apple itself.

So Apple, if you think about it, is only partially competing with Intel. It's more like Apple is competing with Microsoft, Windows, AND Intel as a group; while simultaneously playing hands on the side against AMD and Linux.

The "product" for Apple is the whole computing experience; not just one hardware part. Intel is only one cog in a much larger wheel.

Please continue the discussion everyone I find this quite fascinating even though much of it as well over my head.

In defense of USPS the organization I have a much respect for them the brokerage I worked for, we did bulk of our shipments with them. And compared to UPS and FedEx in courier service we generally have the fewest problems which was remarkable given the sheer amount of mail that we had coming in from them.

Also, it’s unusual for national mail carriers to deliver on the weekends. We’ve always been somewhat unique to get our six day week mail delivery here in the US. But if you want Sunday service too you should go look at UPS and FedEx will charge you for that perk.

I just also wanted to make a comment that their service has indeed worsened but try to see that for why it is. They have had a political hack installed by the last president, Who goes to work every day trying to figure out new ways to run the organization into the ground. A lot like when the president installed an asset stripper to run the EPA I’m sure you would understand why that was done over there, well it’s the same reason here.. So you might be feeling the results of that I hope you will hold the responsible party for that responsible and not the organization.