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Is the M2 really faster than the M1?
- Thread starter Misheemee
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double the bus bandwidth → 100% faster ?!
Double the M2 ( you are shifting the baseline of what is being compared )
“… including the memory controller that delivers 100GB/s of unified memory bandwidth — 50 percent more than M1….”
Apple unveils M2 with breakthrough performance and capabilities
Apple today announced M2, beginning the next generation of Apple silicon designed specifically for the Mac.
www.apple.com
The M2 is 50% increase over the M1 ( ~66 —> 100 is an increase of 50% ( ~33) )
The M1 Pro and Max are well past that.
“… M1 Pro offers up to 200GB/s of memory bandwidth with support for up to 32GB of unified memory. M1 Max delivers up to 400GB/s of memory bandwidth — 2x that of M1 Pro and nearly 6x that of M1 — …”
Introducing M1 Pro and M1 Max: the most powerful chips Apple has ever built
Apple today announced M1 Pro and M1 Max, the next breakthrough chips for the Mac.
www.apple.com
400 / 6 = 66.667 ( same 66GB/s as above )
so the Pro is 3x the M1, And 2x ( 200%) the M2 .
therefore in any memory bandwidth constrained task the current Pro (or Max) will ‘smoke’ the M2 .
Apple did not jump a whole SoC segmentation level with the M2 at all.
the M1 was already at the higher end of LPDDR4X and M2 is at entry end of LPDDR5 . The bus width is the same . There is no room on the parameters to do a game changing jump .
“Some” of the M1 information is definitely wrong, not all.
Also, M2 benchmarks do exist:
Mac14,7 - Geekbench
Benchmark results for a Mac14,7 with an Apple M2 processor.
browser.geekbench.com
Actual tests show the M2 even faster than the graph I found yesterday:
Good to have a glimpse on the sample report.
Some people claim Block A1 & A2 are thunderbolt/usb4 controllers. I would think that's a bit more likely than Secure Enclave.
Interesting idea. The thing is, thunderbolt, usb, and other outside-connecting stuff usually have a separate IC far from the sensitive logic to deal with noisy and potentially damaging electrical conditions.
IIRC from the leaked M1 MacBook Pro schematics/layout/BoM, there were thunderbolt retimer ICs close to where the connectors attach to the mainboard— these sanitize the outside signal and pipe clean signal across the PCB to/from the SoC (though I don’t remember how much protocol stuff they handle). I’d have to dig up the retimer datasheet, but my guess is that @mr_roboto had it mostly right by just calling the PHY I/O blocks SERDES (I think those blocks have some extra protocol-related logic).
TLDR; I don’t think thunderbolt/usb4 stuff is on the SoC, beyond very tiny blocks to handle protocol logic.
So bottom line, M2 is faster than M1, end of story
The question has been answered
The question has been answered
Still have to wait to see which is faster when thermal throttling under sustained load with passive cooling.
You're right about the retimers. There two JHL8040R thunderbolt re-timer chips, one for each port near the side of ports e.g. as shown in M1 MBP logicboard, and as in M1 MBA logicboard.
Re-timers are not controllers. There are no other Intel chips on the PCBs. I would be surprised if the two thunderbolt controllers are not on M1 SoC. Same goes for USB controllers.
Looking at Zen2/Zen3 based Ryzen I/O die (though 12nm), USB control logics aren't tiny. Appear to be occupying a bigger area than PSP which is AMD's version of Secure Enclave.
Some people are so frigging weird. What kind of "gotcha" are you trying to find? The M2 is faster than M1. Not a lot faster, because this is the tail end of the long drawn out 5nm fab process. But it's faster. Not that it even needed to be, because M1 is still plenty fast.
M3 will be a lot faster because of moving to 3nm later next year.
/thread
M3 will be a lot faster because of moving to 3nm later next year.
/thread
Yep. Those blocks probably also contain a PCIe root complex per port, and one of Apple's IOMMUs.
Nah, these things don't need to be on a separate IC. The potential for damage to the SoC is generally mitigated by designing in clamping diodes on the board to shunt spikes above/below the acceptable differential swing to ground or a power rail. Galvanic isolation is provided by putting a capacitor in series with each half of the differential pair. Series caps provide ~infinite ohms impedance at DC and ~0 ohms at GHz, so they block DC current/voltage while allowing signal through.
The one thing not integrated into M1/M2 is the USB1/2 physical layer required to make up a complete USB4 port - USB 3 and above provide backward compatibility by just including a separate differential pair to carry USB1/2 signal. The problem here is that USB1 dates from the late 1990s, and as such uses 3.3V signal levels. You can't do 3.3V in a high performance node like TSMC 5nm, most modern logic process nodes only support 1.8V (or less) I/O. Chip spotters like iFixit have found the necessary separate USB1/2 PHY ICs on Apple Silicon Mac motherboards, but everything else seems to be internal.
Retimers are all about extending "reach" - the length of wire and number of connectors in the signal path. Signal boosters, more or less. Issues corrected include things like equalization, attenuation, and frequency dispersion.
10G and higher through wires is just very difficult, even when the connection is point-to-point on a single circuit board. That's why Apple puts retimers right next to the ports. It's also why longer TB3 cables which support the highest speeds are so much more expensive; they have retimer ICs integrated into each cable head.
Retimers can be protocol aware, but don't have to be.
The blocks for handling protocol logic are much larger than you seem to give them credit for. I mentioned the PCIe root complex above, and RCs are usually relatively large and complex digital blocks. PCIe is literally a networking protocol. For example, it does reliable packet delivery, so root complexes, switches, and endpoints all need to buffer all transmitted packets until the remote end acknowledges correct delivery.
My job involves working with large, expensive FPGAs - think $5000 for a single chip. I once looked at a soft PCIe RC core for a large Xilinx 7 series FPGA. Like most modern FPGAs, it had several hard PCIe RC IP cores, but they didn't support all the PCIe features we needed. We had to reject that idea because once we got a quote and access to some technical docs from the provider of the soft RC core, it turned out the soft core would've filled most of the FPGA's programmable logic fabric by itself, leaving very little for our design.
Yeah, I know what retimers do, how to route differential pairs and control impedances, various ways to protect electronics, etc. I was vague because I didn't think the specifics would be relevant here.
I looked into it, and I admit that PCIe root complexes are way larger than I had thought. So, your theory is that the M2 (and M1) have two root complexes? Maybe it's easier to have two since there are two TB4/USB4 busses, and all other I/O is dedicated to specific devices?
Alternatively, there is still plenty of space at the bottom of the region SystemPlus labeled "Standard Cell Logic" (and a similar region around the bottom of the M2 die shot) to contain the root complex(es). I'm still somewhat dubious that they would misidentify a root complex. PCIe IP isn't exactly new or particularly secret for hardware reverse engineering firms.
Ah, sorry for talking past you then.
Yes, if those SERDES are PCIe SERDES it'd make sense to have the root complex serving them next door.
As to the question of two RCs versus one, I do have to admit it would be normal practice to have a single RC serving both ports. However, Apple might be doing something a bit different - one of their original presentations on PCIe in Apple Silicon showed them dedicating a whole IOMMU to each PCIe device, in order to improve security, and in turn that might mean they've architected a single-port RC with its own IOMMU.
But this is where I'm on pretty shaky ground.
Also, I'd guess that Apple's RC is really just DesignWare, not an in-house RC. Some DW IPs do get hardened for particular nodes, but if they didn't do that here, the RCs could be buried somewhere in the amorphous sea of synthesized and APR'd RTL you can see in M1.
this youtuber did extensive testing with real apps (lightroom, photoshop, final cut) and the base model M2 is barely faster than base model M1
That being said, it could be partially explained by a lack of optimisation for the M2? But if you app is too niche you may never have such optimization happenning anytime.. (i'm thinking about myself with clip studio paint which doesn't seems to care much about macOS)
That being said, it could be partially explained by a lack of optimisation for the M2? But if you app is too niche you may never have such optimization happenning anytime.. (i'm thinking about myself with clip studio paint which doesn't seems to care much about macOS)
I'm not sure that's even really a thing here..
Nothing has really changed that would/could be optimized for (please correct me if wrong ...anyone)
After such a giant leap with the M1 it’s understandable that the next version would have more modest updates. But they did add the silicon for specific use cases such as 8K ProRes.
sooo... there hasn't been any "gotcha's" with the m2? No "rage" about the M1 read/write speed being faster on the base airs? Maybe not so weird after all...😉
Edited to add - "rage" as in "all the rage" or a popular topic
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It could also be due to other things like SSD speed since the comparison is over base models.
It would be nice to see comparisons between models that are more likely to be chosen by people who need performance, like 16/512.
Yes, the base model M2s have about half the SSD performance. Not worth buying over the M1 MBA.
OTOH If you add RAM and SSD capacity to the M2 MacBook you are spending almost as much as you would for the base 14" MBP, a much better (though heavier) laptop.
That's a perfect example of faux rage. No MacBook Air user is taking advantage of M2 read/write speeds let alone M1.
Of course its worth buying over the M1 Air. This logic is absolutely idiotic. This is like saying I need a car to get me to the store, but the BMW is not worth buying over the Ferrari because it can only do 160 and the other can top 200. You're still only going to go 60. MBA users don't care about read/write speeds that already far exceeded their needs.