Agreed. The only downside is, you can't independently pick CPU and GPU options. I don't care as much for GPU power, but I'd still need a 64-core GPU to get the 20-core Apple Silicon CPU.
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M1 Ultra is the last chip based on the M1
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I would say the "final member of the M1 family" doesn't mean final member of the "M1 architecture."
From a practical standpoint, how likely is it Apple took M1 from low to high, then with M2, they'll do a complete reversal and design from high to low?
There cannot be 2x M1 Ultra...there is ultrafusion just in one side
So we have to wait for the M2 for the Mac Pro
The RAM arrangement it will be interesting...some folks kind of manage it , Can’t have four chips surrounded by RAM like now, unless… two chips on one side of the PCB and two on the other one
So we have to wait for the M2 for the Mac Pro
The RAM arrangement it will be interesting...some folks kind of manage it , Can’t have four chips surrounded by RAM like now, unless… two chips on one side of the PCB and two on the other one
Then it will be too late to be competitive as the "M1 architecture " is already 1-year-old as it originates from Apple A14.
Why it would be from high to low? And the order actually does not matter that much. The A14, M1 and M1 Pro/Max are different designs. Only M1 Pro and M1 Max shares large potion of design and the M1 Ultra uses two M1 Max. If it is a sane choice to design an M1 Max instead to put multiple M1 together, it will be a sane choice to make another design for more powerful Mac Pro. Putting 4 Socs together is harder than you think because the interconnection will not be simple.
I'm not convinced that the Ultra isn't the "full die" and that the Max is actually an Ultra cut in half, and the Pro is an Ultra cut in half with part of it lopped off.
The interconnect between two Maxes would be a lot quicker/robust if it were entirely part of the die and not bond wires connecting them.
EDIT: sorry, I didn't notice your assertion that TSMC's 5nm reticle would prevent the chip from being that big. I'm...not convinced of that either. I've recently interviewed with a startup that was talking about making a wafer scale chip (e.g. a design that occupied the entire wafer). My guess is that the size of the interconnect features would be large enough that some error in the reticle placing wouldn't be terribly important since they're just wires that need to line up/overlap and not transistors.
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M1 Max already performs like a 16-core AMD 5950X.
What exactly does the competition have that is at risk of outperforming the M1 Ultra or 2x M1 Ultra?
Because that's how the industry works. Apple is doing it, AMD and Intel have been doing it for decades.
It takes time to develop and build around the A14 Firestorm and Icestorm cores. It takes a couple years to enhance the A15 Avalanche and Blizzard cores.
Workstation chips always come last, desktop and mobile first. It's only today, March 8 that AMD is launching Zen 3 based workstation chips. The architecture was launched in November 2020, same time as M1.
Zen 4 is going to launch later this year and Alder lake for Server and Workstation will launch soon as well. If it is released later than now then it will face stronger opponent and lose its advantage.
The issue is to get 16 cores, you need a 'perfect' die. To get 32 cores you need two perfect dies. And if an Ultra is actually a single piece of silicon (vs. two Maxs put together), that's an even slimmer chance the entire area ends up fully functional so there's even more cost adder.
Plus, they know somebody will pay for the best, so they charge a little more for that, too.
Zen 4 is an architecture. As I mentioned, it'll take about 2 years before it flows up to the workstation and server products. AMD just announced Zen 3 workstation processors, today.
Alder Lake is not for server or workstation. Sapphire Rapids is the correct code name. It won't arrive until later this year and is based on Intel 7.
The HEDT market is DEAD, their Zen 3 Server products (Milan) are in service for almost a year now, and Zen4 Server chips(Genoa) will ship THIS YEAR. The competition is real.
I beginning to believe the Mac Pro Will be the last/first Mac To get the M2 chip! I say they might release this the either Conference or Fall event!
I don't know enough of SoC packaging to answer to this caveats, really. I obviously agree that if the entire interconnect were part of the die it would be faster (but then they'd also have lower yields, even if it does fit inside the reticle, which now I'm unsure about).
The wording on the keynote strongly suggests to me that the interconnect connects two separate dies. They call it 'die to die interconnect', say that it 'connects the two dies', compare it to 'the leading multi-chip interconnect' and say that 'thanks to the magic of the UltraFusion architecture, it behaves like a single chip to software' (all of this starts at about the 27' mark on the keynote video).
Server chips simply don't work well as workstations, ignoring the cost. AMD EPYC is a server product and most motherboards don't even have official Windows 10/11 support becuase they're meant for data centers. You won't find a Thunderbolt 4 port, USB-C, much less HDMI-out.
Mac Pro is a polished, ready to go workstation. A lot of people also buy Mac for macOS.
Theoretically, you could say there's competition, but practically there's none.
??? There are already Alder lake i7 based machines.Zen 4 is an architecture. As I mentioned, it'll take about 2 years before it flows up to the workstation and server products. AMD just announced Zen 3 workstation processors, today.
Alder Lake is not for server or workstation. Sapphire Rapids is the correct code name. It won't arrive until later this year and is based on Intel 7.
Alder Lake is not a workstation product.
Count the cores on Alder Lake then count the cores on M1 Ultra.
What we can confirm is that UltraFusion I a multi-die interconnection archcture so its not impossible that it will be something like this ... because UltraFusion and multi-die seems strange only to waste on one product...
Mac Studio
M1 Ultra Chip (2 M1 Max Chip) using UltraFusion
20 CPU Core
64 GPU Core
128 GB Unified memory
Mac Pro
2xM1 Ultra Chip (4 M1 Max Chip) using UltraFusion
40 CPU Core
128 GPU Core
256 GB Unified memory
Mac Pro
4xM1 Ultra Chip (8 M1 Max Chip) using UltraFusion
80 CPU Core
256 GPU Core
512 GB Unified memory
Mac Pro
6xM1 Ultra Chip (12 M1 Max Chip) using UltraFusion
120 CPU Core
384 GPU Core
768 GB Unified memory
Mac Studio
M1 Ultra Chip (2 M1 Max Chip) using UltraFusion
20 CPU Core
64 GPU Core
128 GB Unified memory
Mac Pro
2xM1 Ultra Chip (4 M1 Max Chip) using UltraFusion
40 CPU Core
128 GPU Core
256 GB Unified memory
Mac Pro
4xM1 Ultra Chip (8 M1 Max Chip) using UltraFusion
80 CPU Core
256 GPU Core
512 GB Unified memory
Mac Pro
6xM1 Ultra Chip (12 M1 Max Chip) using UltraFusion
120 CPU Core
384 GPU Core
768 GB Unified memory
We'll see when somebody decaps it and sees if its a single piece of silicon or not. I rewatched the relevant portion and he said "it connects over 10000 signals", which is vaguely ambiguous. If its 10K wires, it really suggests the interconnect is on the wafer itself between two M1 MAX die. If its referring to an array of SERDES channels that bundles "signals" as packets, serializes them, and deserializes them on the other side, then it seems there's IP out there for that.
Still kind of pricy, it's only $200 to go from 24 to 32 cores on the M1 Max - the 48 core model is a pretty good price to performance ratio ... 64 core less so.