M3 Die Shot suggests display engines take up nearly the same area as P-cores

[ArkSingularity]

According to the M3 annotated die shot images, it appears that each display engine is nearly as large (edit: even larger) in terms of area taken on the die as a P-core , excluding its L2 cache. Of course, this is only a fairly loose way of measuring transistor counts between the two (transistor counts don't always correlate exactly with the area taken on the die), but it's surprising to see that the display engines are this large in silicon.

Intel's chips (with only a tiny fraction of the transistor counts) have long been able to power multiple external displays even on chips that are very small in comparison, so it's clear that Intel has not necessarily been building display engines that are nearly as large in silicon. The very large display engines on Apple Silicon seem to explain why the base level M1/M2/M3 chips only support one external monitor, but I'm curious as to why the display engines are so much larger on Apple Silicon.

I've heard that this might have to do with power consumption (they've probably designed these display engines in such a way that is optimized to use less power rather than for die-area or transistor counts), but I'm admittedly not a chip engineer. Does anyone have more information on the technical reasons behind this? (Just asking out of curiosity)

 

[thenewperson]

I wish I could remember the Asahi guy's Mastodon because I just read his explanation on there a few weeks ago. He first explained it on Twitter (which I remember) but then he deleted his account on there. And yes, it was about power consumption based on his explanation iirc.

 

[altaic]

I wish I could remember the Asahi guy's Mastodon because I just read his explanation on there a few weeks ago. He first explained it on Twitter (which I remember) but then he deleted his account on there. And yes, it was about power consumption based on his explanation iirc.

Here you go: https://social.treehouse.systems/@marcan/111437325851665455

Hardware limit. It's about the number of display controllers. I've mentioned this before: Apple's display controllers are *huge*, almost certainly for power efficiency reasons, and that means they are very expensive so they can't put many of them in a cheap chip.

Also, from a few weeks ago: https://social.treehouse.systems/@marcan/111329025893593939

It's a display controller thing. Apple's display controllers are massive since they optimize for low power use. M3 is like M1/M2, just one external display plus the internal one.

 

[thenewperson]

Here you go: https://social.treehouse.systems/@marcan/111437325851665455

Thanks! I really should get to using my Mastodon seriously to keep track of things 😅

 

[ArkSingularity]

Here you go: https://social.treehouse.systems/@marcan/111437325851665455

It's odd that the display controllers are so large. I know that Apple is able to support 6K displays on each one, but can't Intel chips also do the same? Interesting that they've confirmed the power consumption idea though. If the Asahi guys are saying this, it's probably true.

Still very curious about exactly what they're doing internally from a technical standpoint. My original guess was that they were perhaps having the display buffer sit entirely in silicon to reduce how often the display controller needed to transfer data from RAM (would theoretically help with power consumption), but after some quick handwavy math, I'm not entirely sure how feasible that idea is.

6144 * 3456 pixels times 3 bytes per pixel would be over 63 megabytes, and if we assume 6 transistors per bit, that's 48 transistors per byte of this cache/sram. That would work out to over three billion transistors just for a 6K display buffer alone! (I'm relying on assumptions about what is feasible, but it's safe to say I have my doubts)

Really has me curious about exactly what they're doing in there. It's clearly not my area of expertise. 😂

 

[JPack]

Snapdragon 8c and 8cx support dual 4K external. X Elite will support dual 5K.

Current Intel mobile chips support single 8K60 or quad 4K60.

Let's say Qualcomm and Intel display controllers use more power and M3 is extremely low. This feels like a butterfly keyboard situation where M3 is unreasonably skewed towards power consumption. The feature mix feels wrong. Most MacBook Air consumers aren't going to spend $3,000 for a single 6K monitor or use it to run games with ray tracing.

 

[ArkSingularity]

Snapdragon 8c and 8cx support dual 4K external. X Elite will support dual 5K.

Current Intel mobile chips support single 8K60 or quad 4K60.

Let's say Qualcomm and Intel display controllers use more power and M3 is extremely low. This feels like a butterfly keyboard situation where M3 is unreasonably skewed towards power consumption. The feature mix feels wrong. Most MacBook Air consumers aren't going to spend $3,000 for a single 6K monitor or use it to run games with ray tracing.

Well, I'm mostly interested in the technical differences under the hood that lead to the size difference. The power consumption differences are pretty substantial in real-world use, my Intel laptops couldn't drive external displays without essentially doubling their power consumption and spinning up the fans. This hasn't been the case on the Apple-Silicon Macs (retina screens also have to be considered, which have many more pixels than the average laptop screen and thus need to have fairly efficient display controllers if these laptops want to have great battery life).

Chances are likely that they're using similar display controller technology that they have in the iPhone. Power consumption is extremely important on these kinds of mobile devices, and I imagine they've probably based the Mac display controllers off of the same technology they've been using in the A-series chips (if I had to guess).

 

[JPack]

Well, I'm mostly interested in the technical differences under the hood that lead to the size difference. The power consumption differences are pretty substantial in real-world use, my Intel laptops couldn't drive external displays without essentially doubling their power consumption and spinning up the fans. This hasn't been the case on the Apple-Silicon Macs (retina screens also have to be considered, which have many more pixels than the average laptop screen and thus need to have fairly efficient display controllers if these laptops want to have great battery life).

Chances are likely that they're using similar display controller technology that they have in the iPhone. Power consumption is extremely important on these kinds of mobile devices, and they've probably base the Mac display controllers off of the same technology they've been using in the A-series chips.

Personally, I've never had fans turn on because of external monitors with any recent (10th gen or newer) ThinkPad X1. I have a Dell 5K UW monitor and regularly swap using the built-in KVM between M1/M2 and the ThinkPad. And if the fans did turn on, is that a show stopper? If someone is using an external monitor, chances are, they're plugged in or power is fed through USB-PD.

 

[ArkSingularity]

Personally, I've never had fans turn on because of external monitors with any recent (10th gen or newer) ThinkPad X1. I have a Dell 5K UW monitor and regularly swap using the built-in KVM between M1/M2 and the ThinkPad. And if the fans did turn on, is that a show stopper? If someone is using an external monitor, chances are, they're plugged in or power is fed through USB-PD.

My thinkpad was an 8th gen powering an ultrawide (fan spins up quickly). Definitely was pretty significant of an increase in power consumption, although I've never tried on a 10th gen (which likely is more efficient).

The display controllers they're using also have to power the internal displays, so power consumption does still matter in that sense. I suppose there would be nothing stopping them from designing a second controller that's more die-area optimized for external displays, but the engineering effort to try to redesign a controller probably wouldn't be worth the cost (I'm also admittedly not a chip engineer, so I'm not qualified to comment on what would be required in order to actually do this).

Edit: It appears that this might have been exactly what Apple has done. The base M3 apparently only has one annotated display controller, which seems to suggest that the internal one might potentially be powered by a separate non-annotated one.

 

[leman]

I think it’s exactly what you say, larger memory buffers. Using larger buffers means the DRAM can be kept in low-power state longer, which will slightly reduce the power consumption (and the idle power consumption of AS is ridiculously low).

. The feature mix feels wrong.

I was wondering about the same thing. Low power consumption is very important for the internal display, maybe less so for external ones. Maybe it would make sense to have different types of display controllers - one for power efficient internal display and multiple smaller ones for external displays?

 

[mr_roboto]

Well, I'm mostly interested in the technical differences under the hood that lead to the size difference.

It's memory - you can see it in the die photographs, much of the area of each display controller is SRAM.

You're correct that an entire frame buffer would be too much SRAM to be practical, but there's still scope for power reduction with less than that. The DRAM memory controller and DRAM IO can both sleep to save power, but if you have display refresh constantly hammering on them, they won't be able to. If you put a big(ish) chunk of SRAM in the display refresh pipeline and use it as an intermediate buffer, you can change the display refresh DRAM access pattern to be short periods of very high read bandwidth (refill the buffer) alternating with long periods of nothing (wait until the buffer's almost empty). These gaps give the DRAM subsystem a chance to nap long enough to save power.

If the system is already very busy for other reasons, this has no effect - the DRAM won't be sleeping anyways. But in mostly-idle scenarios, it can reduce the power required to refresh a display.

 

[Allen_Wentz]

My guess is that chip-architecturally Apple is playing component chess thinking many steps ahead, including to smaller denser processes and perhaps to future on-chip activities that Apple has not shared with us. But establishing the flow of processing now.

 

[ArkSingularity]

Looking more closely at the die-shots, and there is another mystery in them: The base M3 only has one display controller, despite having to support two displays (one internal + one external). Furthermore, the M3 Pro only has two controllers and can support three displays (internal + two external), and the M3 Max has four display controllers for five displays (four external + internal).

Assuming these are annotated correctly (and they might not be), it appears that some of these display controllers might in fact be able to drive more than one display, but not all of them are. It's unclear whether there are actually differences between the display controllers, or whether this is an artificial limitation.

We can't necessarily jump to conclusions that it's an artificial limitation either, since Apple still is adding one additional display controller for each additional display after the standard 2 displays (one internal + one external) from the first display controller. It's more likely that the internal display itself is driven by another separate display controller somewhere on the die that isn't annotated.

 

[theorist9]

The feature mix feels wrong. Most MacBook Air consumers aren't going to spend $3,000 for a single 6K monitor or use it to run games with ray tracing.

Agreed. They're more likely to want to run up to two 4k's (or even two 5k's) than a single 6k. And in the busines world, two low-res monitors is pretty standard.

I think it’s exactly what you say, larger memory buffers. Using larger buffers means the DRAM can be kept in low-power state longer, which will slightly reduce the power consumption (and the idle power consumption of AS is ridiculously low).

I was wondering about the same thing. Low power consumption is very important for the internal display, maybe less so for external ones. Maybe it would make sense to have different types of display controllers - one for power efficient internal display and multiple smaller ones for external displays?

It's memory - you can see it in the die photographs, much of the area of each display controller is SRAM.

You're correct that an entire frame buffer would be too much SRAM to be practical, but there's still scope for power reduction with less than that. The DRAM memory controller and DRAM IO can both sleep to save power, but if you have display refresh constantly hammering on them, they won't be able to. If you put a big(ish) chunk of SRAM in the display refresh pipeline and use it as an intermediate buffer, you can change the display refresh DRAM access pattern to be short periods of very high read bandwidth (refill the buffer) alternating with long periods of nothing (wait until the buffer's almost empty). These gaps give the DRAM subsystem a chance to nap long enough to save power.

If the system is already very busy for other reasons, this has no effect - the DRAM won't be sleeping anyways. But in mostly-idle scenarios, it can reduce the power required to refresh a display.

From the specs for the M2 Mini and M2 Studio, we know that the "internal" display controller on the base M2 supports 5k, while those on the M2 Pro and M2 Max each support 4k. [The base M2 needs a more powerful internal controller because it has to drive the 4.5k iMac, while those on the Pro and Max need to drive, at most, the 3456 x 2234 display on the 16" MBP.]

I'd be interested to know how big the 4k controller is. As leman mentioned, since that's the one active on battery, it would need to be particularly efficient.

If it's substantially smaller than the external controller, Apple could have given the base M laptops the ability to drive two external displays, one 6k and one 4k, without significantly increasing the die area.

The M2 Ultra is an interesting case. The M2 Max has 4 external controllers and one internal, allowing it to drive 4 x 6k + 1 x 4k. However, even though the Ultra (presumably) has double the controllers (8 external + 2 internal), it can't do 8 x 6k + 2 x 4k; instead, it's limited to 8 x 4k or 6 x 6k. This is probably due to an I/O limitation: The Max offers 4 x TB, while the Ultra doesn't have 8 x TB (insteed, it's 6 x TB).

 

[Basic75]

The power consumption differences are pretty substantial in real-world use, my Intel laptops couldn't drive external displays without essentially doubling their power consumption and spinning up the fans.

AFAIK that's because the larger Intel MacBook Pros always power up the dGPU when you attach an external display.

 

[theorist9]

Looking more closely at the die-shots, and there is another mystery in them: The base M3 only has one display controller, despite having to support two displays (one internal + one external). Furthermore, the M3 Pro only has two controllers and can support three displays (internal + two external), and the M3 Max has four display controllers for five displays (four external + internal).

Assuming these are annotated correctly, it appears that some of these display controllers might in fact be able to drive more than one display, but not all of them are. It's unclear whether there are actually differences between the display controllers, or whether this is an artificial limitation (I won't jump to conclusions that it's an artificial limitation, since Apple still is adding one additional display controller for each additional display after the standard one internal + one external display from the first display controller. It's more likely that the internal display itself is driven by another separate display controller somewhere on the die that isn't annotated.)

I'd asked @mr_roboto about this earlier (on a different forum), and he explained there are two controllers on the base M chips, one internal and one external, and that the former is typically missed when people do die annotations. I.e., it's there, it's just not labeled.

 

[ArkSingularity]

AFAIK that's because the larger Intel MacBook Pros always power up the dGPU when you attach an external display.

I was actually using a Thinkpad to compare to, which might not necessarily be the most fair comparison. The power consumption difference is very noticeable, but it's possible that there are other factors at play.

 

[ArkSingularity]

I'd asked @mr_roboto about this earlier (on a different forum), and he explained there are two controllers on the base M chips, one internal and one external, and that the former is typically missed when people do die annotations. I.e., it's there, it's just not labeled.

That explains it. That was my suspicion when I saw that, because it wouldn't have made sense for only one of the annotated display controllers to support multiple displays when all of the others are still the same size.

 

[Basic75]

If you put a big(ish) chunk of SRAM in the display refresh pipeline and use it as an intermediate buffer, you can change the display refresh DRAM access pattern to be short periods of very high read bandwidth (refill the buffer) alternating with long periods of nothing (wait until the buffer's almost empty).

How much RAM can they realistically have included? Could it be embedded DRAM instead of SRAM to save space? A 6K frame buffer is around 60MB. If they have 1MB they'd have to wake the system RAM 60*60 times per second. Is that worth it? Though if you're running a 6K display you're probably not on battery power.

 

[ArkSingularity]

How much RAM can they realistically have included? Could it be embedded DRAM instead of SRAM to save space? A 6K frame buffer is around 60MB. If they have 1MB they'd have to wake the system RAM 60*60 times per second. Is that worth it? Though if you're running a 6K display you're probably not on battery power.

I had the same question.

On a related but slightly different note, I also know that Apple does reduce refresh rates when the screen doesn't need to be refreshed. According to iStats menus, both my 13" M1 and my 14" M2 do this, although I have questions about the M1 13" since it doesn't have ProMotion. (It is possible that iStats menus is measuring how often the GPU updates the frame's contents rather than how often the display itself actually gets refreshed, although I do not know for sure and haven't been able to confirm this.)

 

[ondioline]

The Display Engine is more than a simple buffer from what I remember when it was originally introduced. It also handles the refresh rate and anti-aliasing for each display output.

 

[Basic75]

I had the same question.

Here's another one, do they compress that framebuffer cache? And will we ever find out ;-)

 

[ArkSingularity]

Here's another one, do they compress that framebuffer cache? And will we ever find out ;-)

I'm curious now. That's a good question for @name99

 

[Allen_Wentz]

I think it’s exactly what you say, larger memory buffers. Using larger buffers means the DRAM can be kept in low-power state longer, which will slightly reduce the power consumption (and the idle power consumption of AS is ridiculously low).



I was wondering about the same thing. Low power consumption is very important for the internal display, maybe less so for external ones. Maybe it would make sense to have different types of display controllers - one for power efficient internal display and multiple smaller ones for external displays?

Why should power consumption be less relevant for external displays? Saving power is saving power. E.g. my M2MBP drives three 4K external displays plus the internal display whenever I am working. Every bit of added efficiency IMO is a good thing.

 

[Nugat Trailers]

There's a lot of interesting things about the M3 dieshot. Namely how tiny those E-cores are, and how absolutely large the GPU is. Nearly a quarter of the board.