That is a bit backwards. In both cases it is more so "lack of customers using the node" that is the 'problem' more so than an technical issue with the node. Long running leaks of Arrow Lake was always on N3B.
2021
https://www.reddit.com/r/AMD_Stock/comments/p17m8a
2022
Intel Arrow Lake-P GPU confirmed feature up to 320EUs Just a few days ago Intel officially confirmed it will launch Arrow Lake architecture by 2024. This successor to Meteor Lake is now confirmed to utilize a combination of three process nodes. It will also take advantage of Intel’s new die...
videocardz.com
Arrow Lake at one point was suppose to have a more laptop focused variant, but that too probably got the budget chop to chase 20A. And now they likely have neither. ( likely a downclocked desktop variant will target laptops with dGPUs. Like previous generations.)
"... In the case of Core Ultra 5 240F, a change of CPU tiles may also mean a change of fabrication node. The 6+8 version is said to be using Intel 20A, while the 8+16 is rumored to use either Intel 20A or TSMC 3 nm node. ..."
Core Ultra 5 240F, expected to use two versions of the Arrow Lake-S silicon A new rumor suggests Intel will continue its ‘tradition’ to mix silicon dies within the mid-range CPU segment. The next-gen Arrow Lake-S series is on track to debut on the desktop platform this year, introducing the...
videocardz.com
There always was an Arrow Lake die variant that was only on TSMC. In the higher volume subset of the Arrow Lake target market Intel was going to try to squeeze in 20A to cover some of the volume. (incrementally reducing Intel's consumption of TSMC wafers). Why is Intel throwing more money at making a duplicative die on a different process was always the question.
It is Intel 20A that was a 'late addition' add over time. Adding 20A to Arrow Lake was largely a way of throwing extra money at the product. (duplicate dies). Probably in part to help sell customers of Fab foundary services on whether 20A was something they could buy. In that sense, similar 'problem' that N3B has in that almost nobody wants to buy it. Only Apple and Intel bought into N3B (costs ).
Lunar Lake has Lion Cove cores and so does Arrow Lake. Lunar Lake is also more strategic ( laptops which is most of their consumer CPU market). So there always was going to be N3B cores... it was more so whether some Intel fab process might join them or not.
Intel also shifted their N3B wafer starts by a substantial amount of time. So they likely have a fixed amount of N3B wafers that they "have to" buy. If the project volume of LNL/ARL SoC sales is somewhat down that would be there was even less "extra space" to slot in 20A dies to consume. If the pond for 20A product is getting smaller and smaller, then at some point it doesn't make sense to offer the process. Time and effort is better spent on processes that do have relatively high volume customers.
18A has some customers considering it. Getting the 'bugs' out of that one will make a difference to the Fab business. Too slow helping those customers get to market and some of them will 'walk away'. That is a worse outcome than some largely 'ego' thing of slapping duplicative Intel process on Arrow Lake.
Additionally, Intel has relatively limited EUV production capacity. If the Intel 3 server stuff soaks up most of the short term production capacity and the potential 18A customers would soak up even more in 2025 ... would Intel even have resources for a 'side project 20A' runs that took substantive volume away from TSMC? Perhaps not. One reason Intel is over at TSMC for N3B is not their 'process node' deficit. It is because that can't do very high volume production of EUV of any process. ( AMD has been taking server market share away from Intel. The last problem they need now is to turn away some server customers they have left because the Intel 3 server dies are running constrained on availability some desktop only thing is using capacity they need for the short term. ). Intel has to be very careful of not substantively oversubscribing they limited set of EUV systems.