M4+ Chip Generation - Speculation Megathread [MERGED]

[name99]

Has Intel confirmed this? Do you have a link to it?


I measure the success of N3B by the number of companies using it. The rumors were that TSMC customers were waiting for N3E. If the rumors are true and only Apple uses N3B, I would consider N3B a failure.

That seems like a dumb way to measure success ("number of companies using it").

I'd suggest that you view this more in terms of what the node provided for TSMC (in terms of learning, customer satisfaction/retention, and profit)...

 

[kikeman07]

Another GB6 benchmark for the M4 just dropped; a new core architecture upgrade is definitely there! 🚀

https://browser.geekbench.com/v6/cpu/compare/6016039

 

[krell100]

That's quite a jump from the best previous single core score of 3131 in the M3 MacBook Pro, my math makes it about a 21% jump.

 

[DrWojtek]

Another GB6 benchmark for the M4 just dropped; a new core architecture upgrade is definitely there! 🚀

https://browser.geekbench.com/v6/cpu/compare/6016039



View attachment 2376039

Plenty of more scores available now in line with the first one, what a gain! Breaks M3 Pro in ST by a lot and goes toe to toe in MT! This is definitely my next mac!

10% increase in Metal score vs M3.
20% increase in ST score vs M3.
25% increase in MT score vs M3.

 

[DrWojtek]

If it is true that the next Ultra is a custom SoC and not two Max fused together, then I could see Apple skipping M3 and launching the M4 Ultra at WWDC for the Mac Studio (alongside M4 Max) and Mac Pro. I would also expect Apple to refresh the Mac Mini with M4 and M4 Pro at WWDC, as well.

Then in the Fall the MacBook Pro line would be updated to M4 / M4 Pro / M4 Max as by then yields should be good enough to meet the significantly higher demand for the laptops vis-a-vis the desktops.

If I’m guessing, there is no Ultra on the horizon. This ”custom SoC” was actually the M4. But no one thought M4 would come so soon, so people thought it was M3 Ultra.

And if that is the case there are M4 macs coming this WWDC.

 

[leman]

Because the M series SoCs use the A series as their foundation. So M4 uses A18 as the foundation and M5 will use A19. With A18 not even shipping until September, I do not see Apple pushing M5 out before A19 and A19 will not ship until September 2025.

Ah, there I disagree. I see this more as Apple using the same IP for both A-series and M-series chips rather than A-series being the foundation of M-series. We already saw the pattern broke with A16 (for which there was no corresponding M-series chip), and now for the first time we have an M-series chip released before A-series. I do not see it is at all as certain that the A18 will use the same IP as M4. It seems that the CPU just got a big boost (with steaming mode SVE/SME), so not much will likely change there, but I could see more GPU improvements coming later this year.

Overall, it would appear that Apple is assuming a more aggressive iteration cycle, shipping IP when it is ready instead of waiting for large feature bundles. This could be a good strategy for motivating the customers and improving sales.

 

[leman]

And if that is the case there are M4 macs coming this WWDC.

Since M4 CPU introduces some features relevant to pro workloads (SME CPU extensions), it would make perfect sense for the next prosumer Macs to be released with this architecture.

 

[scottrichardson]

holy crap those benchmarks are crazy fast for the single core. WOW.

 

[CWallace]

If I’m guessing, there is no Ultra on the horizon. This ”custom SoC” was actually the M4. But no one thought M4 would come so soon, so people thought it was M3 Ultra.

I could see Apple skipping M3 Ultra since desktops do not make up much of Apple's sales so Mac Studio and Mac Pro could limp along with M2 Max and M2 Ultra. While the M3 Max is faster in some CPU benchmarks and tasks, M2 Ultra will still have the edge in GPU performance.

 

[Xiao_Xi]

There are on-going small tweaks to AMX every year.

Could Apple have replaced AMX with SME in M4?

FCLC (@fclc@mast.hpc.social)

@bshanks@mastodon.social @never_released@mastodon.social @marcan@treehouse.systems @dougall@mastodon.social @saagar@saagarjha.com they haven’t; this would be a deprecation of AMX in favour of SME

mast.hpc.social

 

[DaniTheFox]

If I’m guessing, there is no Ultra on the horizon. This ”custom SoC” was actually the M4. But no one thought M4 would come so soon, so people thought it was M3 Ultra.

And if that is the case there are M4 macs coming this WWDC.

I thought that too. But then is there still a place for a M3 Ultra?

 

[DaniTheFox]

Ah, there I disagree. I see this more as Apple using the same IP for both A-series and M-series chips rather than A-series being the foundation of M-series. We already saw the pattern broke with A16 (for which there was no corresponding M-series chip), and now for the first time we have an M-series chip released before A-series. I do not see it is at all as certain that the A18 will use the same IP as M4. It seems that the CPU just got a big boost (with steaming mode SVE/SME), so not much will likely change there, but I could see more GPU improvements coming later this year.

Overall, it would appear that Apple is assuming a more aggressive iteration cycle, shipping IP when it is ready instead of waiting for large feature bundles. This could be a good strategy for motivating the customers and improving sales.

I see a similar concept. They have building blocks of different parts of a SoC. In several states of functionality. When they have to freeze the design, it could be a block more advanced would be available just a little time latter. Bad luck. But you have to freeze once. You can’t forever.

 

[dugbug]

I thought that too. But then is there still a place for a M3 Ultra?

If I were a betting man I would say the M3 was a stop-gap on an expensive node with yield issues and so no, no M3 ultra. I would not be surprised in the least (now) to see an M4 ultra at WWDC. But who can figure apple out.

 

[leman]

Could Apple have replaced AMX with SME in M4?

I'd say they are pretty much the same thing. AMX instructions were already very similar to SME/SVE streaming mode, it's likely that Apple fixed the last few differences and taught the decoder to parse SME instructions. I wouldn't be surprised if AMX instructions are still supported though, there were at least a few interesting things Apple included that SME didn't support if I remember correctly.

 

[DaniTheFox]

If I were a betting man I would say the M3 was a stop-gap on an expensive node with yield issues and so no, no M3 ultra. I would not be surprised in the least (now) to see an M4 ultra at WWDC. But who can figure apple out.

WOW. You think they have the total family together. What is it then with all the analyst talking about end of 2024, and beginning of 2025.
I mean they haven’t seen the M4 in the iPad Pro only when the stumble with there feet over it. So it is possible. Apple need AI powerhouses.

 

[nikhsub1]

So the way Apple is going now - get this, CPU upgrades from TSMC are coming so fast, that they are literally skipping generations in products. If we look at the tea leaves, this 'could' be the start of a trend - certain products will skip every odd generation chip?

 

[name99]

Could Apple have replaced AMX with SME in M4?

FCLC (@fclc@mast.hpc.social)

@bshanks@mastodon.social @never_released@mastodon.social @marcan@treehouse.systems @dougall@mastodon.social @saagar@saagarjha.com they haven’t; this would be a deprecation of AMX in favour of SME

mast.hpc.social

It appears that this is indeed the case!

This morning has been lots of back and forth between a few of looking at different types of evidence. And here's my long writeup:

Apple Debuts Next-Generation M4 Chip

The basic consensus right now, after a morning of frantic back and forth on Twitter and other platforms (I don't have time to give the details justifying this consensus) is that, as far as *CPU* goes - clock is about 8% faster, presumably at essentially flat power (no mean feat) - IPC gain is a...

forums.macrumors.com

 

[name99]

I'd say they are pretty much the same thing. AMX instructions were already very similar to SME/SVE streaming mode, it's likely that Apple fixed the last few differences and taught the decoder to parse SME instructions. I wouldn't be surprised if AMX instructions are still supported though, there were at least a few interesting things Apple included that SME didn't support if I remember correctly.

Yes, I agree, hardwarewise and performancewise.
Main difference is now all that AMX goodness is available to assembly writers and the compiler directly.

Main QUESTION is whether NEON is now SVE, and if so whether it's 128b SVE or 256b SVE.

 

[mr_roboto]

So the way Apple is going now - get this, CPU upgrades from TSMC are coming so fast, that they are literally skipping generations in products. If we look at the tea leaves, this 'could' be the start of a trend - certain products will skip every odd generation chip?

TSMC doesn't deliver CPU upgrades to Apple, they deliver new chip manufacturing process nodes. Apple designs their own chips, including the CPU, to be manufactured in TSMC fabs.

I would be very hesitant to project future patterns based on this. It could easily just be the result of some project schedules slipping, and others not.

Also worth keeping in mind that these chips are the outcome of dependencies between complex projects in two separate organizations (*). Stuff happens! It's honestly amazing that Apple has delivered a new A series chip for every iPhone launch for so long. That's probably the only thing you can count on - last I looked iPhone was still Apple's biggest and most important revenue source, so their chip team is almost certainly still operating under the constraint that priority #1 is always the chip for next fall's iPhone refresh.

* - actually more than two, as Apple doesn't design absolutely everything in their chips themselves. For example, they rely on Synopsys DesignWare IP for lots of I/O features.

 

[falainber]

That seems like a dumb way to measure success ("number of companies using it").

I'd suggest that you view this more in terms of what the node provided for TSMC (in terms of learning, customer satisfaction/retention, and profit)...

The companies use test chips (plenty of those) for learning when they develop the tech process. N3B was developed for commercial use and as such it was a failure. Of course TSMC will do the post-mortem and learn something but this is not different from Intel learning something with 14+, 14++, 14+++ etc.

 

[falainber]

So the way Apple is going now - get this, CPU upgrades from TSMC are coming so fast, that they are literally skipping generations in products. If we look at the tea leaves, this 'could' be the start of a trend - certain products will skip every odd generation chip?

M4 is not a full fledged new generation product. While Apple is free to use whatever naming scheme they want, the reality is that M4 does not use a new architecture. It uses a slightly modified (to boost yield and reduce cost) tech process. All semi companies but Apple simply refused to use N3B because it was a dud. Apple was in a pickle because they had to stick with the annual iPhone release schedule. But they knew the process was bad, so, while still working on the N3B based chips they probably started re-spinning the layout for N3E. The small time gap between M3 and M4 is not an indication of some sort of acceleration of the development/release cycle.

 

[bcortens]

M4 is not a full fledged new generation product. While Apple is free to use whatever naming scheme they want, the reality is that M4 does not use a new architecture. It uses a slightly modified (to boost yield and reduce cost) tech process. All semi companies but Apple simply refused to use N3B because it was a dud. Apple was in a pickle because they had to stick with the annual iPhone release schedule. But they knew the process was bad, so, while still working on the N3B based chips they probably started re-spinning the layout for N3E. The small time gap between M3 and M4 is not an indication of some sort of acceleration of the development/release cycle.

Given that the supposed improvements on N3E vs N3B according to TSMC are only 2-5% and yet we see a 10% clock speed uplift along with small IPC improvements suggest you’re quite wrong about this. Unless TSMC is lying to it’s customers (which would get them in a lot of trouble) M4 has an updated core architecture to enable higher clocks and (slightly) improved IPC.

 

[falainber]

Given that the supposed improvements on N3E vs N3B according to TSMC are only 2-5% and yet we see a 10% clock speed uplift along with small IPC improvements suggest you’re quite wrong about this. Unless TSMC is lying to it’s customers (which would get them in a lot of trouble) M4 has an updated core architecture to enable higher clocks and (slightly) improved IPC.

Clock speed depends on many factors, not just architecture. Apple explains what's new in M4 here and new architecture is not listed. Unless Apple is so modest as to not mention the new CPU architecture (while boasting about the new display engine), it's not a new architecture.

 

[name99]

I'd say they are pretty much the same thing. AMX instructions were already very similar to SME/SVE streaming mode, it's likely that Apple fixed the last few differences and taught the decoder to parse SME instructions. I wouldn't be surprised if AMX instructions are still supported though, there were at least a few interesting things Apple included that SME didn't support if I remember correctly.

I'm not so sure.

If you look at SME (especially the latest SME2.1 stuff, eg
https://reviews.llvm.org/D137571 )
so much of it, in hindsight, seems motivated by AMX functionality. For example LUTI2 and LUTI4 seem to match AMX lookup table stuff [since AMX1, apparently to support quantized weights] along with the strided 2 and 4 vector loads that were added to M3 AMX.

So maybe the combination "pretty much everything we want is in the latest SME" and "we never promised direct AMX would work, use Accelerate like we told you to" covers everything? Presumably you want to free up those instruction codes as soon as possible, so that they can be reused for the next round of Apple experimentation...

Again, in retrospect, if you look at the sequence of SVE2 updates, things like SVE2p1 many of them do kinda look like Apple (along with many outsiders, but I expect Apple's voice matters most) trying to get things fixed. Maybe it was all just a question of "once you make these seven changes to SVE/SME we're willing to adopt it" played out over a few years?

 

[name99]

M4 is not a full fledged new generation product. While Apple is free to use whatever naming scheme they want, the reality is that M4 does not use a new architecture. It uses a slightly modified (to boost yield and reduce cost) tech process. All semi companies but Apple simply refused to use N3B because it was a dud. Apple was in a pickle because they had to stick with the annual iPhone release schedule. But they knew the process was bad, so, while still working on the N3B based chips they probably started re-spinning the layout for N3E. The small time gap between M3 and M4 is not an indication of some sort of acceleration of the development/release cycle.

So you consider addition of SME "not indicative of a new [CPU] architecture"?
OK then.